The Dry Resist War.Original analysis

The AI chip race is usually described through GPUs and HBM. But underneath that visible battle sits a quieter manufacturing problem: turning fragile EUV images into clean, repeatable, low-defect patterns on silicon.

The AI chip race is usually described as a fight over GPUs, HBM, and advanced packaging. That is the visible layer. Underneath it sits a quieter manufacturing problem. How do you keep printing smaller, cleaner, more reliable patterns on silicon when features are approaching atomic scale?

EUV lithography solved one part of the scaling problem. It gave chipmakers shorter-wavelength light and removed the need for some brutal multi-patterning flows. But EUV did not remove the physics of pattern transfer. The scanner exposes the wafer. The resist absorbs the photons. The image becomes a chemical or physical pattern. That pattern must survive development. Then it must be transferred into real device layers through etch and deposition.

At advanced nodes, the resist is no longer a boring chemical layer. It becomes a yield bottleneck.

That is why Lam Research’s Aether dry resist matters.

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I. The 2020 thesis

In May 2020, Dylan Patel published a piece on SemiAnalysis arguing that Lam’s dry resist work could grow into a multi-billion dollar business as EUV adoption made traditional wet patterning flows harder to scale.¹ The argument was structural. Wet resist worked beautifully for DUV and for early EUV layers. As features shrank, stochastic effects, line collapse, line-edge roughness, and the cruel dose-versus-defectivity tradeoff began to bite harder. Lam, an equipment company anchored in deposition, etch, and clean, was trying to expand its role inside the EUV patterning module.

I revisited that piece because the question it asked is no longer hypothetical. Production tools are being placed in fabs. Memory makers are picking horses. High-NA EUV is starting to arrive. Patterning has moved from a back-of-the-paper concern into the front of every advanced fab’s roadmap.

The piece was conservative in 2020. It assumed steady AI demand and the standard advanced-node cadence. Neither of those held. The actual 2024 to 2026 AI capex cycle made the patterning question more urgent and more strategic.

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II. The 2026 update

Six years later the thesis is no longer about whether dry resist could matter. It is about which layers it wins, how fast it scales, and how much of the broader patterning module Lam can take.

Four concrete moves on the public record:

• In January 2025, Lam said its Aether dry photoresist had been adopted as production tool of record by a leading memory manufacturer for advanced DRAM processes.²
• Two weeks earlier, Lam announced an imec qualification establishing a 28nm pitch directly printed in dry photoresist for back-end-of-line logic at 2nm and below, with extendibility flagged toward High-NA EUV.³
• In September 2025, Lam and JSR/Inpria entered a cross-licensing and collaboration agreement covering EUV patterning materials, metal oxide resists, dry resist, High-NA EUV, and advanced films, signalling that the materials side of the ecosystem is being structurally aligned around the new flows.⁵
• In March 2026, IBM and Lam announced a five-year collaboration focused on sub-1nm logic scaling, High-NA EUV, novel materials, and fabrication processes.⁶⁷

The macro picture matches. ASML’s 2025 annual report frames AI as the structural driver of EUV demand and projects advanced Logic EUV lithography spending growing at 10 to 20% CAGR from 2025 to 2030, and DRAM EUV lithography spending at 15 to 25% CAGR over the same period.⁸ SEMI projects global semiconductor equipment sales reaching a record $156 billion in 2027, with DRAM equipment growing 15.4% in 2025, 15.1% in 2026, and 7.8% in 2027 on HBM and advanced node demand for AI and data centers.⁹

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III. What wet resist does, simply

Wet resist is the boring, useful workhorse of patterning. A liquid resist is spun onto the wafer as a thin film. The wafer is exposed to light. A wet chemistry develops the pattern by dissolving away either the exposed or unexposed regions. Etch and deposition then transfer the pattern into the device layers.

It works because the ecosystem is enormous. Track tools, resist chemistries, develop chemistries, inspection, and rework flows are all mature. For DUV and most early EUV layers, the wet flow is fast, reliable, and well understood. It is not going anywhere for the bulk of the wafer.

It gets harder at advanced pitches for a small set of physically stubborn reasons. EUV photons are scarce per unit area, so dose has to climb to expose reliably. Higher dose costs throughput and money. Wet development can warp narrow features through capillary forces, which produces line collapse and pattern degradation. Edge roughness becomes a meaningful fraction of the linewidth. Stochastic events, where a few missing photons or chemical events ruin a single feature, accumulate into yield loss. None of this kills wet resist. All of it raises the cost of staying on it as pitches shrink.

Diagram 01 · Traditional wet resist flow

01

Spin coat

Liquid resist applied to a spinning wafer.

02

EUV exposure

Scanner exposes the resist image.

03

Wet development

Chemistry dissolves the pattern.

04

Etch transfer

Pattern is etched into the device layer.

Wet flow. Mature, fast, well understood. Capillary forces, dose limits, and stochastic effects start to bite at extreme pitches.

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IV. What dry resist changes

Lam’s Aether replaces the liquid resist with a vacuum-deposited film built from metal-organic compounds. Lam says these compounds absorb three to five times more EUV light than traditional carbon-based resist materials.⁴ The development step is also dry, performed in vacuum, which removes the capillary forces that collapse the smallest wet-developed lines.

The downstream chain matters more than any one of those steps. Better photon absorption can reduce the EUV dose needed for a given fidelity, which protects scanner throughput. Lower dose at constant fidelity is a direct cost win, since the scanner is the most expensive tool in the fab. Dry development reduces line collapse and a class of wet-chemistry defects. Fewer process steps reduces the opportunities for pattern degradation between exposure and etch. Lam also frames Aether as integrating cleanly with its Nimbus underlayer and dry plasma develop tools, which extends the company’s role from a single resist step to a fuller patterning module.

Diagram 02 · Dry resist flow

01

Dry deposition

Vacuum-deposited metal-organic film.

02

EUV exposure

Higher EUV absorption per nm.

03

Dry development

No capillary forces, lower collapse.

04

Etch transfer

Pattern is etched into the device layer.

Dry flow. Vacuum deposition. Higher EUV absorption. Dry develop. The shape of the flow is the same. The physics of each step is different.

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V. Why this matters for AI chips

Patterning matters because every advanced chip starts as a patterning problem. The GPU on the headlines, the HBM stacks around it, the interposer underneath, the DRAM in the memory module, the NAND in the storage tier, the I/O dies on the package: every one of them has to be printed first, then transferred, then yielded.

AI demand pushes on every one of those layers at once. Frontier accelerators need leading-edge logic. HBM and DRAM need advanced memory scaling. Advanced packaging needs more interposer real estate. Every additional EUV layer is also another patterning step. If those steps cost too much, or yield too poorly, the AI roadmap shifts.

The AI boom does not only pull on Nvidia. It pulls on the entire manufacturing stack.

Diagram 03 · The pattern transfer stack

06

EUV scanner exposure

ASML

05

Resist (wet or dry, metal oxide)

Resist makers / Lam

04

Underlayer / hardmask (e.g. Nimbus)

Lam

03

Develop (wet track or dry plasma)

TEL / Lam

02

Etch / deposition transfer

Lam / AMAT / TEL

01

Inspection & metrology

KLA

Pattern transfer is a stack, not a step. Aether attacks layers 05, 04, and 03 in a way that compounds across the rest.

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VI. DRAM and HBM make it interesting

The 2020 thesis was largely a logic story. EUV had just arrived at TSMC and Samsung leading-edge logic. The 2026 version is also a memory story. That is what made me revisit the question.

Three signals matter. Lam said Aether was adopted as production tool of record by a leading memory manufacturer for advanced DRAM in January 2025.² ASML expects DRAM EUV lithography spending to compound at 15 to 25 percent annually from 2025 to 2030.⁸ SEMI projects DRAM equipment growth driven by HBM ramps and advanced DRAM nodes for AI and data center demand.⁹

If advanced memory uses more EUV and more difficult patterning, then dry resist could matter beyond logic. The careful version of the claim is the right one. Dry resist may not dominate every memory layer. It could win selected critical layers where dose, defectivity, pattern fidelity, and cost of ownership justify adoption. That is still a large prize, because critical layers are where the cycle time and yield damage compounds.

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VII. High-NA EUV raises the stakes

High-NA EUV improves imaging resolution by increasing the numerical aperture of the scanner optics. Smaller features become printable. The downside is that smaller features make pattern transfer harder, not easier. A better scanner is not enough if the resist and the etch stack cannot preserve what the scanner exposed.

ASML said in May 2026 that the first commercial chips made with its High-NA EUV machines were expected within months, with Intel, Samsung, and SK hynix moving forward and TSMC remaining more cautious about adoption timing.¹⁰ IBM and Lam framed their five-year collaboration explicitly around High-NA EUV process flows for sub-1nm logic, novel materials, and fabrication processes.⁶⁷

High-NA can print smaller. Dry resist helps make smaller printable features actually manufacturable.

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VIII. TSMC and the low-NA extension

TSMC has reportedly been working to extend current low-NA EUV tools further instead of moving to High-NA immediately, while continuing to push its own process and packaging roadmap.¹² The schedule on the public record is structural. N2 entered high-volume manufacturing in late 2025, N2P and A16 are scheduled for the second half of 2026, A14 is planned for 2028, and the CoWoS family continues to expand to support AI systems.¹¹

That does not weaken the dry resist thesis. It may strengthen it. If fabs want to extend low-NA EUV longer, they need more process integration around the scanner. Better resist. Better underlayers. Better etch. Better deposition. Better metrology. Better defect control. Each of those is a slot Lam wants to occupy, and Aether is the most visible new piece.

The same logic applies in the other direction. If High-NA adoption accelerates faster than expected at Intel, Samsung, and SK hynix, the patterning challenge there is even harder, and the case for dry resist is also stronger. Either path keeps the patterning module strategic.

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IX. Why this is a Lam business model story

Lam does not sell EUV scanners. ASML does. Lam sells the process tools around the scanner: deposition, etch, clean, dry development, films, and now a meaningful slice of the resist-related patterning module. Aether is important to Lam not only because it improves yield. It is important because it gives Lam a chance to take a larger slice of the EUV patterning module, alongside an ecosystem partner stack in materials.

Lam frames Aether as a suite of EUV solutions, including dry photoresist, the Nimbus underlayer, and dry plasma develop, with claims about reduced scanner dose, lower defectivity, lower waste, and lower cost. The company has publicly discussed a roughly $1.5 billion cumulative incremental revenue target across the patterning portfolio over the next five years.⁷ That is a meaningful slice of a single equipment company’s growth, even before you assume any second-order effects from a dry-resist transition.

This is a semiconductor value-chain analysis, not investment advice. The point is that the structure of who captures value is changing. Some of that value will sit with ASML for scanners. Some will sit with TEL for traditional track and etch. Some will sit with KLA for metrology and inspection. Some will sit with materials makers like JSR/Inpria. The new question is how much of the patterning module migrates toward Lam if dry resist scales.

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X. Value chain map

This is a value-chain map, not investment advice. The point is to make the shape of the dependency visible. The AI memory and logic build is a multi-vendor effort across lithography, materials, deposition, etch, packaging, and metrology, and dry resist is one new link, not the whole chain.

Diagram 04 · The value chain

Lithography

ASML. EUV and High-NA EUV scanners.

Dry resist / process integration

Lam Research. Aether, Nimbus underlayer, dry plasma develop.

Wet develop & track

Tokyo Electron and related ecosystem.

Materials

JSR, Inpria, and other resist and underlayer makers.

Foundries

TSMC, Samsung, Intel Foundry.

Memory makers

Samsung, SK hynix, Micron.

Research ecosystem

imec, IBM Albany, NY CREATES.

Inspection & metrology

KLA and others. The yield witnesses.

Advanced packaging

TSMC CoWoS, ASE, Amkor and others.

Customers

Nvidia, AMD, hyperscaler ASIC teams, AI accelerator startups.

This is a value-chain map, not investment advice. Each box can become a bottleneck. Dry resist is one of the newer links, sitting between lithography and etch.

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Quick terms

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XI. What could break the thesis

A serious piece needs counterarguments. The case for dry resist has more than one honest failure mode.

The correct claim is not that dry resist replaces everything. The correct claim is that as EUV is pushed harder by AI-era logic and memory, dry resist has become one of the most important process technologies to watch.

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XII. The dry resist war

The AI era is making chip manufacturing more complex, not less. The industry needs more advanced logic, more DRAM, more HBM, more advanced packaging, more power efficiency, and more yield from every wafer.

EUV is central to that roadmap, but EUV alone is not enough. At the smallest dimensions, the bottleneck moves into the messy middle. Resist. Underlayers. Development. Etch. Pattern transfer. Defectivity. Cost of ownership. That is where Lam is making its bet.

It will be won by the companies that can turn fragile nanoscale patterns into real, repeatable, low-defect device structures. That is the dry resist war. And in the AI era, it matters much more than it did in 2020.

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This is Essay No. 013. The topics: intelligence, AI, systems, knowledge, and the questions underneath the questions everyone else is asking. If you read this far and disagreed with any part of it, write to me. I read everything.