The Memory Oligopoly Became AI’s Toll Booth.Original analysisNot investment advice

For decades, memory was treated as the boring commodity layer of computing. DRAM and NAND mattered, but the attention went to CPUs, GPUs, foundries, lithography, and leading-edge nodes. Memory was noticed mostly when prices spiked, and even then the story was treated as a cycle to be ridden, not a structure to be analysed. That view is now broken. In 2021, Micron said it would not add DRAM or NAND wafers for the foreseeable future. At the time it looked like ordinary capital discipline. In 2026, it looks like the opening chapter of the AI memory squeeze.

Memory used to be the part of the system people forgot. In the AI era, memory is where the system starts to break.

That single line is the spine of this essay. The old memory cycle was about oversupply. The new AI memory cycle is about allocation. Who gets HBM. Who gets server DRAM. Who gets enterprise SSDs. Who gets long-term contracts. That is the new power structure, and it is not the cycle anyone was trained to model.

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1. What the 2021 warning got right

The starting point for this essay is an uploaded 2021 SemiAnalysis piece on the memory oligopoly. It is a useful historical anchor, not a final verdict, and the specific framing is worth restating in its own words before grading it.¹

Read carefully, the 2021 piece was not the claim that any particular price would hold for any particular quarter. It was a market-structure claim. A consolidated industry with three leading-edge DRAM players, an even smaller NAND group after Intel exited, and an explicit commitment from one of those players not to expand wafer output, was always going to behave differently from a fragmented commodity market the next time demand surprised on the upside. That is the part of the 2021 framing that aged well. No SemiAnalysis text, charts, screenshots, or images are reproduced here. The original piece is treated only as cited historical framing.

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2. From commodity cycle to allocation market

The classic memory cycle was simple, and for decades it more or less worked. Prices rise. Suppliers add capacity. Supply arrives late. Prices crash. Capex gets cut. Weak players suffer. Strong players survive. The cycle restarts. Anyone who had spent a career around the DRAM industry could draw this diagram from memory.

The AI memory cycle keeps some of those moves and changes others. The number of aggressive suppliers has come down. DRAM has only three leading-edge players. NAND is consolidating around a smaller set as well. HBM consumes scarce advanced DRAM capacity and advanced packaging capacity at the same time. Cleanroom expansions take years, not quarters. New fabs are expensive and slow even before you factor in equipment delivery, qualification, and yield ramp. AI customers, unlike traditional PC and smartphone buyers, are willing to sign strategic agreements and long-term supply deals to lock in capacity.

The old memory cycle was about oversupply. The new AI memory cycle is about allocation.

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3. The 2026 proof: Micron’s results

If the 2021 framing was structural, the 2026 financials are the structural test. Micron’s Q2 FY2026 print is striking on every line.² Revenue of USD 23.86 billion. GAAP gross margin of 74.4%. Diluted EPS of USD 12.07. Q3 FY2026 revenue guided to USD 33.5 billion with gross margin guidance around 81%. Those are not the numbers a normal commodity industry posts. They are the numbers a market where demand outruns capacity, and where the suppliers can allocate to the highest-value customers, posts when the supply line tightens.

Micron’s own framing in the prepared remarks is unambiguous about what is driving this.³ Memory has, in management’s words, become a strategic asset for customers in the AI era. AI demand is pulling data-centre DRAM and NAND bit TAM above 50% of total industry TAM for the first time in calendar 2026, in Micron’s framing. Both AI and traditional server demand are described as constrained by inadequate DRAM and NAND supply. These are management statements, not independent estimates. Treat them as direction, not gospel. The direction is the part to keep.

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4. This is not only HBM

It is tempting to read all of this as an HBM story. HBM is the high-bandwidth memory stacked beside the GPU or accelerator. It exists because AI accelerators are useless if data cannot be fed to them fast enough to keep the math units busy. HBM is the visible memory shortage, the one Nvidia keeps name-checking on earnings calls, the one that supports the most aggressive long-term agreements anywhere in the supply chain.

That part is real. Micron began volume shipments of HBM4 36GB 12-high products in Q1 calendar 2026, framed as part of the qualification flow into Nvidia’s Vera Rubin platform, and has been sampling 48GB 16-high HBM4 as the next step.³ Those are company claims, not third-party measurements, but they describe a roadmap that is being pulled forward, not pushed back.

The trap is to treat HBM as the entire memory story. Micron’s prepared remarks are explicit that LPDRAM, DDR DRAM, and SSDs are all critical across new AI inference architectures, and that AI demand is moving the whole DRAM and NAND mix toward data-centre customers.³ HBM gets the headlines. The hidden bottleneck is the rest of the stack.

HBM is the visible bottleneck. The hidden bottleneck is the whole memory stack.

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5. NAND enters the AI story

NAND is the part of the AI memory story that even careful readers sometimes miss. NAND is not HBM. NAND is not the memory beside the GPU. NAND is the persistent storage layer further out. For most of the previous decade, NAND was a consumer story: phones, PCs, consumer SSDs, embedded products. AI changed that.

Micron’s prepared remarks describe the shift in plain terms. NAND bit demand in the data centre is accelerating because of AI use cases such as vector databases and KV-cache offload. SSDs are taking a growing share of capacity storage tiers. Data-centre NAND revenue at Micron more than doubled sequentially in the most recent quarter. NAND demand is described as significantly above available supply for the foreseeable future.³ The capacity to fix that is years out: Micron’s prepared remarks point to mid-calendar 2027 for initial wafer output at the first Idaho fab, and the second half of calendar 2028 for the new Singapore NAND fab. Singapore advanced packaging for HBM is expected to contribute meaningfully in calendar 2027.³

The use cases are not hypothetical. Training data sits on enterprise SSDs in the same racks as the accelerators. Model checkpoints land somewhere durable and fast. Retrieval systems and vector databases stress NAND read patterns more than any classical workload ever did. KV-cache offload, where parts of the LLM attention cache spill out of DRAM into fast storage, is now a real workload in inference clusters. AI data lakes sit on top of NAND. QLC NAND, marketed as the high-capacity medium for AI storage, is in particular demand. None of this looks like a phone factory cycle.

AI does not only need fast memory beside the GPU. It also needs an ocean of storage around the cluster.

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6. Pricing proves the squeeze

The clearest tell that this is an allocation market, not just a noisy cycle, is what is happening to contract pricing. TrendForce’s March 2026 forecast frames Q2 2026 conventional DRAM contract prices as rising approximately 58% to 63% quarter over quarter, and NAND Flash contract prices as rising approximately 70% to 75% quarter over quarter. DRAM suppliers are reallocating capacity toward HBM and server applications. NAND capacity is increasingly allocated to enterprise SSDs while consumer applications scale back. TrendForce flags that substantial new production capacity is unlikely until late 2027 or 2028.⁴

Read those numbers carefully. They are research-firm estimates, not contracts, and quarterly memory prices do not move in clean straight lines. The shape, however, is what matters. Allocation is the operative word. The highest-value AI customers get supply first. Lower-margin segments get squeezed. PCs are squeezed. Smartphones are squeezed. Consumer SSDs are squeezed. Automotive and industrial buyers are squeezed. Even weak end-consumer demand does not necessarily stop price increases when supply is being redirected to AI.

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7. ASML and TSMC show the same macro shift

The memory squeeze does not sit inside the memory industry by itself. It sits inside a broader semiconductor reality that two other companies describe more frankly than most. ASML’s 2026 AGM framing is that AI compute demand has accelerated since 2010 and outpaced Moore’s Law, and that Moore’s Law alone is not sufficient to meet future training compute requirements. ASML frames the answer as 2D scaling plus 3D integration, with customers stepping up medium-term capacity plans, and explicitly says that customer ramp will be aggressive to address a supply-limited market in 2026 to 2027 and possibly beyond.⁵

TSMC’s 2026 Technology Symposium framing is the package side of the same story. TSMC says it is expanding CoWoS because AI needs more compute and more memory in a single package, and gives a specific roadmap.⁶ Five-and-a-half-reticle-size CoWoS in production today. A 14-reticle-size CoWoS planned by 2028 that is expected to integrate roughly ten large compute dies and twenty HBM stacks. Those are TSMC company claims, not independent benchmarks. The direction is what matters. The AI system of the future is not just one bigger chip. It is a memory-hungry package and cluster: more compute dies, more HBM stacks, more data movement, more storage, more power, more cooling, more packaging.

The AI system of the future is not one bigger chip. It is a memory-hungry package and cluster.

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8. Why the oligopoly matters

Now the structural part. DRAM is concentrated. Three suppliers control the overwhelming majority of revenue, and an even smaller subset of capacity is leading-edge HBM-capable. When demand surprises to the upside, that structure changes how the market behaves. It moves the conversation from spot pricing toward allocation and long-term agreements. It puts the supplier on the other side of the table from where they sat in the consumer-era memory cycle.

TrendForce’s Q3 2025 DRAM revenue share is one way to see the structure plainly. SK hynix at 33.2%. Samsung at 32.6%. Micron at 25.7%. The big three together accounting for over 91% of DRAM revenue.⁷ Different sources slice this by bit, wafer, or revenue, and the numbers shift around, but the shape of the market is the part to keep.

A fragmented commodity market behaves one way. A concentrated memory market in an AI shortage behaves another way. The 2026 results are not magic. They are what happens when supply discipline meets a demand environment the original capex plans were never sized for.

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9. China is the counterweight

None of this implies the oligopoly is permanent. The most interesting counterweight is China. CXMT is trying to challenge the leading-edge DRAM incumbents. YMTC is pushing in NAND under sanctions. High memory prices are exactly the conditions that invite capacity, subsidies, and challengers, and China has both the strategic incentive and the willingness to absorb poor economics to reduce memory imports.

The honest read is that this matters more for the medium term than the next quarter. Leading-edge DRAM, HBM, NAND scale, yields, packaging, and customer qualification are hard. Reaching credible production share in DDR5, HBM, or qualifying with major hyperscalers is several rungs harder than reaching domestic share in mature DRAM nodes. The same caveat applies in NAND. The structural risk to the oligopoly thesis is real. It is also slower than the headlines suggest. A separate essay on this site discusses YMTC and the China NAND story in more detail, including the role of export controls and domestic equipment substitution.

The memory oligopoly is powerful in 2026 because AI exposed how hard memory capacity is to replace quickly. But high prices also invite the next wave of challengers, and the policy environment in which those challengers operate is not the same one the incumbents grew up in.

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10. The timeline

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11. Risks and limits

None of this implies memory cycles are dead, that incumbents are invincible, or that today’s prices will hold forever. A serious memory thesis in an AI shortage has to carry a serious risk list.

The point is not that memory cycles are dead. The point is that AI has changed this cycle’s structure. The next downturn, when it comes, will land on a more concentrated supply base with longer customer agreements and a different mix of end demand than the last one did. That changes the shape of the cycle, not its existence.

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12. Evidence ledger

Because this essay sits between an uploaded 2021 thesis and a 2026 reading, the load-bearing evidence is gathered here, paired with source and a one-line note on why it matters.

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13. Final verdict

In 2021, Micron’s “no new wafers” comment looked like disciplined capex. In 2026, it looks like the opening chapter of the AI memory squeeze. AI did not just increase memory demand. It made memory strategic. It turned supply into allocation. It turned the memory oligopoly into a toll booth that sits between AI accelerators and useful work.

The future is not the absence of cycles. The future is a cycle whose shape, customer base, allocation logic, and supplier set are not the ones the industry was trained on. Hyperscalers signing strategic agreements. HBM consuming the leading edge. NAND pulled toward enterprise SSDs. PCs and smartphones squeezed at the margin. New fabs years out. Domestic challengers slowly closing technological gaps. None of this is permanent. All of it is structural.

Memory used to be the part of the system people forgot. In the AI era, memory is where the system starts to break.

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Sources & footnotes

This essay treats the uploaded 2021 SemiAnalysis article as a cited historical anchor. Specific 2026 claims come from Micron investor materials, TrendForce, ASML, and TSMC. Market-share figures are estimates and vary by source. No third-party charts, screenshots, or logos are reproduced. This is not investment advice.