The Open ISA Talent Bet.Original analysisNot investment advice
The 2021 Rivos article was right to follow the people. High-performance CPUs are not built by instruction sets alone. They are built by teams. In 2026, the story has matured: Rivos became a full-stack AI infrastructure bet, combining RISC-V CPUs, a data-parallel accelerator, DDR/HBM memory architecture, software-defined hardware, and datacenter software partnerships. Meta’s move to acquire Rivos shows the real meaning of RISC-V in the AI era. It is not just an open ISA. It is a way for hyperscalers to control more of the compute stack.
In 2021, the story looked simple.
A new RISC-V startup had appeared. It had no famous benchmark. No shipping server chip. No public product roadmap. No proven datacenter ecosystem. But it had something more important: people.
The uploaded SemiAnalysis article identified a remarkable talent cluster — senior CPU architects and leaders from Apple, Google, Marvell / Cavium, Qualcomm, Intel, AMD, DEC, SiByte, P.A. Semi, Broadcom, and MIPS.1 The author compared the moment to Nuvia, the ex-Apple CPU startup Qualcomm acquired for roughly USD 1.4 billion, and argued that this new RISC-V company could become the first truly high-performance RISC-V design.1
That was the right instinct. But the 2026 version of the story is bigger. Rivos was never only about RISC-V being open. It was about what happens when elite CPU talent meets an open ISA at the exact moment hyperscalers want more control over AI infrastructure.
High-performance CPUs are not built by an ISA. They are built by teams that know how to turn an ISA into a shipping system.
1. The 2021 thesis was really about people
The uploaded SemiAnalysis piece was not mainly about RISC-V ideology.1 It was about unusually strong CPU talent, reported by name and by lineage.
The article walked through the cluster carefully. Brian Campbell, with a background spanning SiByte, Broadcom, P.A. Semi, and Apple. Belli Kuttanna, with a background spanning Texas Instruments, Motorola, Sun Microsystems, Intel, Qualcomm, Intel Capital, the evaluation of companies including SiFive, BlueStacks, and Ayar Labs. Mark Hayter, with a background spanning DEC, SiByte, Broadcom, P.A. Semi, Apple, Agnilux, and Google. Tse-Yu Yeh, with a background spanning Intel, SiByte / Broadcom, P.A. Semi, and Apple. Ken Dockser, with a background across DEC, NexGen, MIPS, VLSI, IBM, Qualcomm Centriq, Cloud AI 100, and the RISC-V board.1 The article noted additional contributors from Apple, Google, Cavium / Marvell, Intel, AMD, Xeon Phi, and JEDEC-related work.1
The article’s framing was that high-performance CPU design is not a matter of choosing the right ISA. It is a matter of putting together a team that has shipped real CPUs, real microarchitecture, real verification flows, real physical design, and real platform bring-up. The article compared Rivos to Nuvia at a similar early stage and judged Rivos to be even more stacked with talent.1
The bet was not “RISC-V is free.” The bet was “this is the kind of team that can make RISC-V serious.”
2. Why ISA is not enough
RISC-V is an instruction set architecture. It defines what software can ask a processor to do. It does not, by itself, make any of that fast. A high-performance CPU is the rest of the iceberg under the ISA.
An open ISA gives freedom. It does not give performance for free. Every layer above the ISA — microarchitecture, physical design, firmware, compiler, OS, platform — has to be done well. That is exactly what the 2021 article’s talent thesis was pointing at, even though it was wrapped around an ISA-flavoured headline.
An open ISA gives freedom. It does not give performance for free.
3. Rivos became the test case
By 2024, the anonymous talent migration story had become a funded datacenter hardware company. Rivos disclosed it had raised more than USD 250 million in Series A-3 funding, targeting data analytics and generative AI markets, with the round supporting tape-out of its first silicon product, manufacturing operations, platform hardware, software engineering, and support functions.2 The disclosed investor list included Matrix Capital Management, Intel Capital, MediaTek, Dell Technologies Capital, Walden Catalyst, and others.2
Reuters covered the same round, framing Rivos as a RISC-V startup developing an AI-oriented server chip with both CPU and AI accelerator elements, and as one of a generation of startups trying to challenge the Nvidia + CUDA model from a different direction.3
High-performance RISC-V is not a hobbyist architecture problem. It is a full-stack company-building problem.
4. The product became CPU plus accelerator
The detail that matters most about Rivos in 2024 is that the product was never described as a CPU on its own. Rivos’ own funding announcement described power-optimised chips with high-performance server-class RISC-V CPUs combined with a Data Parallel Accelerator optimised for large language models and data analytics, with the architecture sharing a uniform memory across DDR DRAM and HBM, and targeting models and databases requiring terabytes of memory.2
This is a more interesting position than “new RISC-V CPU vendor.” It says the team thought the binding constraint on AI workloads was the relationship between CPU, accelerator, and memory — not the ISA on the CPU side.2
Rivos is not trying to make RISC-V a nicer CPU instruction set. It is trying to make RISC-V part of an AI datacenter platform.
5. Software is the make-or-break layer
Reuters’ reporting on the 2024 funding made another point that is easy to miss. Rivos’ CEO described a software-first approach to the company — looking at software before silicon, rather than building silicon first and software later.3 The company has used “software-defined hardware” framing to describe its product positioning.2
Recompile-not-redesign: when workloads change, the path of least resistance should be the toolchain, not a new chip generation.
The deeper logic is workload velocity. AI workloads change quickly. The software stack must reach the hardware through compilers, libraries, frameworks, and existing programming models. If the hardware is only fast for last year’s workload, fast does not matter.
The software stack is where RISC-V stops being an ISA and starts becoming a platform.
6. Canonical and Ubuntu matter more than they sound
The most underrated piece of the 2024-2025 Rivos story is the Canonical partnership. Canonical and Rivos announced a collaboration to enhance RISC-V readiness in Ubuntu for the datacenter, including optimised packages targeting Rivos platforms, RVA23 profile support, and enterprise-grade reliability and scalability framing.4
That sounds dry, but it is not. A datacenter CPU needs an OS, kernel support, packages, drivers, firmware, compilers, security updates, virtualization, monitoring, and enterprise reliability. None of that exists by default for a new ISA. It exists because someone builds and maintains it.
No one deploys an ISA in a datacenter. They deploy a platform.
7. RVA23 is RISC-V growing up
The other piece of the 2024 RISC-V story that matters for Rivos is RVA23. RISC-V International ratified the RVA23 profile in October 2024 as the next-generation profile for 64-bit RISC-V application processors, aligning them around a common feature set for running rich operating systems and modern software.5 The Vector extension and the Hypervisor extension are described as key mandatory components of the profile, and the profile targets AI / ML, cryptography, and enterprise OS / software portability.5
A toolbox
RISC-V’s extension model is a strength. It is also a fragmentation surface. Without an agreed feature set, every silicon vendor risks shipping a slightly different RISC-V that needs slightly different software.
A platform
RVA23 ratifies a common feature set for 64-bit application processors, with Vector and Hypervisor extensions among the mandatory components, improving software portability across vendors.5
The point is not that fragmentation is solved by a single profile. It is that RISC-V’s governance is moving from a permissive toolbox toward a platform with shared expectations. That is what real datacenter operators need before they consider any open ISA for production at scale.
RVA23 is RISC-V trying to become less like a toolbox and more like a platform.
8. The datacenter ecosystem is becoming more real
Profiles are one part. Server-class platform standards are another. RISC-V International’s 2025 Annual Report describes ratification of Server SoC and Boot requirements, with a RISC-V Server Platform specification expected by end of 2026, intended to standardise hardware and firmware requirements for enterprise OS and software consistency.6 The same materials describe native RISC-V support in ACPI 6.6 and continued progress on cloud / server ecosystem readiness.6
Scaleway’s public write-ups describe practical RISC-V cloud / server deployments, including the real-world issues of boot, OS, provisioning, and software integration that any production deployment encounters.7 The reading is not that RISC-V has arrived in the datacenter. The reading is that the basic plumbing is being built.
Datacenter RISC-V is not one chip away. It is one ecosystem away.
9. Meta made the thesis obvious
The acquisition announcement is the part that turned an interesting startup story into a strategic story. Reuters reported in September 2025 that Meta intended to acquire Rivos, with the deal framed as strengthening Meta’s in-house semiconductor efforts and connected in the reporting to Meta’s broader MTIA programme and to its dependence on Nvidia for AI chips.8 Meta’s statement, per the Reuters write-up, described Rivos as bringing expertise in full-stack AI systems, and as a RISC-V-focused company.8
Outside law-firm and investor communications subsequently described a definitive agreement, with Rivos framed as a developer of high-performance, power-efficient server solutions built on RISC-V, and with the deal positioned around helping Meta control more of its AI infrastructure.9
Read the acquisition as a hyperscaler signal, not as a RISC-V victory lap.
Meta acquiring Rivos shows that a hyperscaler with significant AI ambitions sees value in owning a high-performance RISC-V CPU and AI accelerator team. It does not, by itself, prove that RISC-V is ready as a broad commercial datacenter CPU platform. Rivos may end up powering Meta-internal infrastructure rather than a wide-market product line.89
RISC-V becomes valuable when it becomes a control surface for hyperscalers.
10. Why hyperscalers care about RISC-V
Hyperscaler interest in RISC-V is best understood as a set of independent levers, not a single ideology. AI infrastructure cost, dependency on Nvidia, memory bandwidth and data movement, power efficiency, fleet-scale optimisation, custom workloads, software control, architectural flexibility, and supply-chain leverage are all in play.
For hyperscalers, RISC-V is not ideology. It is leverage on cost, software alignment, accelerator integration, memory architecture, and supply chain.
RISC-V does not automatically solve performance, software, or ecosystem problems. It gives hyperscalers more freedom to try. That is the actual product. The acquisition signal from Meta is a direct read of that product.
For hyperscalers, RISC-V is not ideology. It is leverage.
11. Nvidia and SiFive validate the control-plane angle
The other 2026 signal worth foregrounding is the SiFive / Nvidia NVLink relationship. Reuters reported in January 2026 that SiFive will integrate Nvidia’s NVLink technology into future RISC-V designs, describing SiFive as the first RISC-V chip-design company to integrate NVLink, with products not expected until 2027 or later.10 SiFive’s own announcement framed this as a coherent high-bandwidth interconnect for connecting RISC-V platforms directly to Nvidia GPUs and accelerators in large-scale AI deployments.11
This does not mean Nvidia is switching to RISC-V. It means RISC-V is becoming acceptable as part of serious AI infrastructure control-plane designs. Combined with Meta acquiring Rivos and Canonical building Ubuntu support, the pattern is more consistent than any single announcement.
Even Nvidia is treating RISC-V as a possible control-plane architecture for AI systems.
12. The China angle is real, but not the whole story
China’s RISC-V push
Reuters reported in March 2025 that China planned guidance to encourage nationwide RISC-V use, framed as a way to reduce dependence on Western-owned technology, with the architecture seen as usable across smartphones, embedded systems, and AI-server CPUs.12
That is real and worth tracking. But it is not the main Rivos story, and it is not the main reason hyperscalers like Meta would acquire a high-performance RISC-V team. Sovereignty and hyperscaler control are different motivations that happen to point at the same ISA.
The cleanest way to read 2026 RISC-V momentum is as a coalition of different actors using the same ISA for different reasons.
RISC-V is not one story. It is a shared escape hatch for many different kinds of control.
13. Why RISC-V still has to prove itself
The narrative arc above is positive enough that it is worth restating the limits clearly. RISC-V still has to prove itself in production datacenters at scale. x86 and Arm have mature server ecosystems. Nvidia dominates AI software and systems. Custom accelerators are expensive. Tape-outs can fail. HBM supply is constrained. Performance per watt must be proven in real workloads. Enterprise software compatibility is hard. Datacenter buyers need reliability and support, not promising benchmarks.
Profiles like RVA23 reduce fragmentation but do not eliminate it.5 Hyperscaler custom silicon can take many product generations to mature. Meta’s acquisition of Rivos may produce internal infrastructure first and a broad commercial platform much later, if at all. None of this argues against RISC-V’s direction. It argues for honesty about the timeline.
Rivos proves that RISC-V can attract talent and buyers. It does not yet prove that RISC-V has become a broad datacenter CPU platform.
14. The actual 2026 thesis
The correct claim is not “RISC-V will replace x86 and Arm everywhere.” That language is too crude.
The correct claim is more structural. Rivos showed that high-performance RISC-V becomes strategically real when three things come together: elite CPU talent, full-stack software, and a hyperscaler-scale customer. The 2021 SemiAnalysis article was right to follow the talent migration from Apple, Google, Qualcomm, Intel, AMD, Marvell, and others.1 The 2026 update is bigger. Rivos became a CPU-plus-accelerator-plus-software platform aimed at AI and data analytics,2 then became strategically important enough for Meta to acquire.8 RISC-V’s datacenter future is not about being free. It is about giving powerful companies more control over architecture, acceleration, memory, and software.
“Rivos is no longer only a RISC-V story. It is a hyperscaler control-of-stack story that happens to ride on an open ISA.”
15. What could break the thesis
The thesis is that elite CPU talent plus an open ISA plus a hyperscaler-scale customer makes high-performance RISC-V strategically real. There are honest reasons that reading could overshoot.
- Limited production proof. RISC-V still has little high-volume, high-performance production datacenter deployment to point at.
- x86 / Arm maturity. Mature server ecosystems on x86 and Arm have decades of tooling, libraries, and operational habit behind them.
- Nvidia’s software lead. Nvidia dominates AI software and rack-scale systems; an alternative CPU does not automatically displace this.
- Acquisition absorption. Meta may use Rivos as internal talent and silicon rather than build a broad commercial platform.8
- CPU + accelerator complexity. Co-designing CPU, accelerator, and memory in a usable platform is genuinely hard.
- Software portability gap. RVA23 reduces fragmentation, but software portability across RISC-V implementations is still a real risk.5
- HBM and memory costs. HBM-heavy memory architectures depend on constrained supply and pricing.
- Generational maturity. Hyperscaler custom silicon can take several generations to be competitive on TCO.
- Risk that Rivos proves talent value, not RISC-V value. The acquisition may end up being about the team, not the ISA.1
Rivos may prove that RISC-V attracts elite teams and hyperscalers before it proves RISC-V can become a broad datacenter platform.
16. What could break the bear case
There are equally honest reasons the bear case could be too dark.
- Elite talent density. Rivos attracted a cluster of CPU architects who have repeatedly shipped real, high-end CPUs at other companies.1
- Real funding. A round of more than USD 250 million in Series A-3 capital is serious for a CPU + accelerator startup.2
- AI-first scope. Rivos targeted AI and data analytics, not only embedded cores or hobbyist designs.2
- CPU + accelerator + memory. Building around CPU + accelerator + uniform DDR / HBM memory is the right shape for AI infrastructure.2
- Software-first culture. A software-defined-hardware framing matches how AI workloads actually evolve.3
- OS-level support. Canonical-led RISC-V readiness in Ubuntu pushes RISC-V toward real datacenter deployment.4
- Profile maturation. RVA23 reduces fragmentation and improves portability across vendors.5
- Server platform direction. RISC-V Server Platform spec and ACPI 6.6 support move RISC-V toward enterprise-grade plumbing.6
- Hyperscaler acquisition. Meta’s move adds workload, capital, and time horizon at hyperscaler scale.8
- NVLink-attached RISC-V. SiFive integrating NVLink puts RISC-V inside the conversation for AI control-plane and host CPU roles.1011
- Multi-actor demand. Hyperscalers, sovereign ecosystems, and custom-silicon teams all want different things from the same ISA.12
Rivos proves the opposite of the old RISC-V stereotype: this is no longer only about cheap embedded cores.
17. What to watch
The honest position is that the open ISA bet is in mid-build. These are the signals that will tell us where it actually lands.
- Whether Meta publicly integrates Rivos into MTIA8
- Rivos team retention after the acquisition closes8
- Meta’s next MTIA generation cadence
- Whether Meta uses RISC-V in CPUs, accelerators, control processors, or full AI systems
- Rivos software stack survival inside Meta workflows
- Canonical / Ubuntu RISC-V progress4
- RVA23 adoption in real silicon5
- RISC-V Server Platform specification progress6
- ACPI / UEFI / server boot standardisation6
- SiFive / Nvidia NVLink product timeline10
- RISC-V cloud server deployments (e.g., Scaleway)7
- China RISC-V policy implementation12
- RISC-V in AI servers vs embedded / control-plane roles
- Arm server momentum (Neoverse cadence and design wins)
- x86 server roadmap (Intel and AMD)
- Nvidia Grace / Blackwell / Rubin platform integration
- Whether hyperscalers use RISC-V for control, host CPUs, or accelerators
- Whether RISC-V picks up real production datacenter workloads at scale
18. The open ISA talent bet
The 2021 Rivos article was right to follow the people.1 High-performance CPUs are not built by instruction sets alone. They are built by teams.
In 2026, the story has matured. Rivos became a full-stack AI infrastructure bet: RISC-V CPUs, a data-parallel accelerator, DDR / HBM memory architecture, software-defined hardware, and datacenter software partnerships.234 Meta’s move to acquire Rivos shows the real meaning of RISC-V in the AI era.89
It is not just an open ISA. It is a way for hyperscalers to control more of the compute stack.
19. Glossary
- RISC-V
- Open instruction set architecture maintained by RISC-V International.
- ISA
- Instruction set architecture; the contract between software and hardware.
- CPU microarchitecture
- The internal design that implements the ISA in silicon.
- RVA23
- RISC-V application processor profile for richer OS / software portability, ratified October 2024.
- Vector extension
- RISC-V extension for vectorised math workloads.
- Hypervisor extension
- RISC-V extension supporting virtualization.
- GPGPU
- General-purpose GPU-style accelerator for parallel workloads.
- Data Parallel Accelerator
- Rivos’ accelerator concept for LLMs and data analytics.
- DDR DRAM
- Standard system memory.
- HBM
- High-bandwidth memory used near accelerators.
- Uniform memory
- Architecture where CPU and accelerator operate over a shared memory model.
- MTIA
- Meta Training and Inference Accelerator.
- NVLink
- Nvidia high-speed interconnect for CPUs, GPUs, and accelerators.
- Hyperscaler
- Very large cloud or internet company operating massive datacenter infrastructure.
- Software-defined hardware
- Hardware designed around software programmability and workload flexibility.
- Recompile-not-redesign
- The idea that workloads can adapt through software recompilation rather than a new chip design.
- Firmware
- Low-level software that initialises hardware before the OS boots.
- ACPI
- System interface standard used by operating systems to discover and manage hardware.
This piece is original 2026 analysis. It uses the uploaded 2021 SemiAnalysis article only as a cited historical anchor for the talent thesis, framed in this essay’s own words. Specific numbers and claims are sourced from Rivos’ own funding disclosures, Reuters reporting, RISC-V International materials, Canonical’s partnership announcement, SiFive’s NVLink announcement, and Scaleway’s public RISC-V server write-up. No SemiAnalysis text, charts, or images are reproduced. No third-party logos are used. This is not investment advice. No specific Meta, Nvidia, Arm, Intel, AMD, Qualcomm, or other security is being recommended.
1 Uploaded SemiAnalysis PDF, Dylan Patel (SemiAnalysis), August 2021. A Chip Off The Old Block? New RISC-V Startup Garners Many Senior CPU Architects From Apple, Google, Marvell, Qualcomm, Intel, and AMD. Used in this essay only as a historical anchor for the 2021 talent thesis, framed in the essay’s own words. The article reported the talent cluster (including Brian Campbell, Belli Kuttanna, Mark Hayter, Tse-Yu Yeh, Ken Dockser, and additional contributors with backgrounds at Apple, Google, Cavium / Marvell, Intel, AMD, Xeon Phi, and JEDEC-related work), compared the startup to Nuvia, noted Qualcomm’s ~USD 1.4B Nuvia acquisition, and argued the startup could become the first truly high-performance RISC-V design. Skepticism of existing SiFive high-performance claims at the time is also from the article. Not reproduced.
2 Rivos, 2024 funding announcement via BusinessWire. Rivos Raises More Than $250M Targeting Data Analytics and Generative AI Markets. Used for: more than USD 250M Series A-3; data analytics and generative AI target; first silicon tape-out; manufacturing operations, platform hardware, software engineering, and support functions; CPU + Data Parallel Accelerator framing; DDR / HBM uniform memory architecture; software-defined hardware positioning; named investors (Matrix Capital Management, Intel Capital, MediaTek, Dell Technologies Capital, Walden Catalyst, and others). Treated as Rivos’ own disclosure rather than independent verification.
3 Reuters, April 2024. Startup Rivos raises $250 million to develop RISC-V AI chips. Used for the ~USD 250M raise, AI-oriented server chip framing, CPU + AI accelerator description, software-first approach attributed to CEO Puneet Kumar (software-before-silicon framing), and the broader framing as one of a generation of startups working against the Nvidia / CUDA dominance pattern from a different direction.
4 Canonical and Rivos partnership, posted via RISC-V International. Rivos and Canonical partner to deliver scalable RISC-V solutions in datacenters. Used for: RISC-V readiness in Ubuntu for the datacenter; optimised packages targeting Rivos platforms; RVA23 profile support; and the enterprise-grade reliability / scalability framing.
5 RISC-V International, October 2024. RISC-V announces ratification of the RVA23 profile standard. Used for: RVA23 ratification, 64-bit application processor alignment, Vector extension and Hypervisor extension as key mandatory components, AI / ML / cryptography / enterprise OS and software workload targeting, and the framing of RVA23 as a portability improvement across implementations.
6 RISC-V International 2025 Annual Report (PDF). RISC-V Annual Report 2025. Used for: ratification of Server SoC and Boot requirements; a RISC-V Server Platform specification expected by end of 2026; native RISC-V support in ACPI 6.6; and the broader datacenter readiness / cloud / server ecosystem progress framing.
7 Scaleway. RISC-V servers in the cloud. Used for: a real-world RISC-V cloud / server deployment write-up, including practical issues of boot, OS, provisioning, and software integration. Scope is treated as illustrative, not as evidence of broad scale.
8 Reuters, September 2025. Meta to buy chip startup Rivos in AI effort, source says. Used for: Meta’s intent to acquire Rivos; the framing as strengthening Meta’s in-house semiconductor efforts; Rivos described as a RISC-V-focused company; Meta’s framing of Rivos as bringing expertise in full-stack AI systems; and the broader context of Meta’s MTIA programme and Nvidia dependence on AI chips. Treated as Reuters / Meta framing.
9 Outside counsel / investor communications. Latham & Watkins advises Meta in acquisition of Rivos. Used for: confirmation of a definitive agreement framing, Rivos described as a developer of high-performance, power-efficient server solutions built on RISC-V, and the positioning of the deal as helping Meta control more of its AI infrastructure. Treated as professional-services / investor communications context, not as independent technical verification.
10 Reuters, January 2026. SiFive to adopt Nvidia technology for speedy links between chips. Used for: SiFive integrating Nvidia NVLink technology into future RISC-V designs, the description of SiFive as the first RISC-V chip-design company to integrate NVLink, the framing of NVLink as a high-bandwidth interconnect for AI datacenters where many chips must communicate, and the statement that products are not expected until 2027 or later.
11 SiFive, 2026 official announcement. SiFive and Nvidia NVLink Fusion in the datacenter. Used for SiFive’s own framing of a coherent high-bandwidth interconnect, reduced latency, and connecting RISC-V platforms directly to Nvidia GPUs and accelerators in large-scale AI deployments. Treated as SiFive’s own positioning rather than independent benchmarking.
12 Reuters, March 2025. China to publish policy to boost RISC-V chip use nationwide, sources say. Used for: China planning guidance to encourage nationwide RISC-V use, framed as reducing dependence on Western-owned technology, with the architecture seen as usable from smartphone chips to AI-server CPUs. Treated as Reuters / policy reporting, not as confirmation of deployment scale.
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- The Custom AI Hardware Trap · on Tesla Dojo and why custom AI hardware is decided at the system level.
- The Package Became the Computer · on package-scale AI compute as the new design surface.
- The Bubble That Became Infrastructure · on Nvidia’s ecosystem advantage from 2021 to 2026.
- Accelerated Computing Atlas · interactive atlas of the Nvidia accelerated-computing ecosystem.