Ayar Labs Was Early on Optical I/O. Now It Has to Prove CPO Can Ship at AI Scale. Ayar Labs TeraPHY SuperNova UCIe Optical I/O Co-packaged optics Silicon photonics Nvidia CPO TSMC COUPE Rack-scale AI
AI is not limited only by how fast chips compute. It is increasingly limited by how efficiently chips talk. Ayar Labs saw the I/O wall early. The next test is manufacturing, packaging, cooling, servicing, and hyperscale deployment.
- Historical context: what the 2022 article got right
- The I/O wall is now an AI infrastructure problem
- TeraPHY plus external light was the architecture
- Micro-ring modulators are the beauty and the risk
- From promise to production attempt
- UCIe makes Ayar easier to integrate
- Alchip and TSMC make the story more serious
- Wiwynn shows the rack-scale deployment problem
- Nvidia validates CPO, but adoption is staged
- The market is moving, but Ayar is not alone
- What Ayar must prove
- Switch CPO vs accelerator-package optical I/O
- Why this matters for AI infrastructure
- Evidence ledger
- Risks and limitations
- Bottom line
- Glossary
- Sources and method notes
- In 2022, Ayar Labs was focused on the real bottleneck: data movement between chips, packages, boards, racks, and data centers.
- The old article argued that electrical I/O was becoming power-hungry and pin-limited as compute scaled.
- Ayar's architecture used TeraPHY optical I/O chiplets, micro-ring modulators, and external lasers to move optics closer to compute.
- By 2026, the market has validated optical I/O: Nvidia is productising CPO switches, TSMC is developing COUPE, and Ayar has partnerships with Alchip and Wiwynn.
- The hard question is no longer whether optics are useful. It is whether co-packaged optics can be manufactured, packaged, cooled, serviced, and deployed at AI scale.
Section 1 · Historical frameWhat the 2022 article got right
The 2022 SemiAnalysis piece, Ayar Labs and the Co-Packaged Optics Revolution, framed Ayar as a hardware startup attacking the I/O wall.[1] Compute was scaling faster than package and off-chip communication. Electrical I/O was becoming increasingly expensive in power and area. Processors were spending more time waiting for data than computing. Ayar's approach was to move optical communication directly into the package, alongside CPUs, GPUs, FPGAs, ASICs, and accelerators. The article highlighted strategic investors and partners such as GlobalFoundries, Intel, HPE, Nvidia, Lockheed Martin, and Applied Materials, and walked through the GF 45CLO photonics process, Intel's earlier proof-of-concept co-packaged photonics tile work with FPGAs, HPE's HPC interconnect collaboration, and Nvidia's strategic investment.[1]
- "The case for in-package optical I/O," with package pin limits and rising off-chip I/O power.
- Electrical interconnect energy and bandwidth penalties as distance increases.
- Optical I/O redefining the CPU socket, moving toward a rack-scale socket.
- Monolithic in-package optical I/O concept with TeraPHY chiplets beside CPU, GPU, FPGA, or SoC.
- Optical I/O system architecture with TeraPHY CMOS optical I/O chips, single-mode fiber, and external light sources.
- Micro-ring modulators, monolithic electronics integration, scalable manufacturing, packaging, lasers, and standards.
- External laser strategy and why serviceability matters for co-packaged optics.
Ayar's insight was not "make optics faster." It was "move optics close enough to compute that the system architecture changes."
Section 2 · The I/O wallFrom compute problem to AI infrastructure problem
AI infrastructure is usually framed as a compute problem. The next bottleneck is communication. Larger AI models require more accelerators. More accelerators require more data movement. More data movement increases power, latency, heat, and system complexity. Electrical I/O is efficient over very short distances but becomes expensive as distance increases. Optical I/O can provide longer reach, high bandwidth density, and better power efficiency for scale-up and scale-out systems. The 2022 piece visualised that trade-off across pages 3, 4, and 6, including the idea that optical I/O could redefine the CPU socket into a rack-scale socket.[1]
AI was not going to be limited only by how fast chips compute. It was going to be limited by how efficiently chips talk.
Section 3 · ArchitectureTeraPHY plus external light
Ayar's core system is not just one photonics chip. It is an optical I/O architecture combining TeraPHY optical I/O chiplets, SuperNova remote light sources, micro-ring modulators, single-mode fiber, UCIe interfaces, and an external laser strategy.[1][4] The external laser model matters because lasers are among the more failure-prone parts of optical systems. With pluggable optics, a failed laser or transceiver can be replaced from the front panel. With co-packaged optics, a failure inside the package is much harder to service. Keeping the light source external is an explicit design choice for serviceability and reliability.[1]
Ayar separated the light source from the optical I/O engine because CPO only works if it can be serviced like infrastructure, not treated like a lab demo.
Section 4 · Micro-ringsThe beauty and the risk
Micro-ring modulators are the heart of the density story. They are compact, energy efficient, and well suited to packing many optical channels into a small area, which is why Ayar's bandwidth-density framing rests on them.[1] They are also notoriously sensitive to manufacturing variation and temperature. Tiny dimensional differences shift wavelength behavior. Temperature drift can pull a ring off resonance. Tuning, monitoring, and control loops have to compensate at the chip level, the package level, and the system level. The trade-off is real: micro-rings enable the architecture, and they also make production reliability harder.
- Compact footprint per channel.
- Dense WDM channel counts in small areas.
- Energy-efficient modulation.
- Well suited to many parallel optical lanes.
- Enables high bandwidth density at the package edge.
- Wavelength sensitivity to manufacturing variation.
- Process variation across wafers and packages.
- Temperature drift in real systems.
- Tuning and control complexity.
- Test and yield burden at production volumes.
Micro-rings are why Ayar's density story is exciting. They are also why production reliability matters so much.
Section 5 · From promise to productionThe 2026 update
Ayar's funding trajectory captures the shift. The 2024 Series D raised US$155 million from investors including AMD Ventures, Intel Capital, and Nvidia, bringing total funding to US$370 million at a valuation above US$1 billion.[2] In 2026, Ayar closed a US$500 million Series E to scale high-volume production and test capacity, expand global operations including a Hsinchu, Taiwan office, strengthen ecosystem partnerships, and accelerate CPO deployment.[3] The shape of the company has changed. In 2022 Ayar was a promising technical bet. In 2026 Ayar is trying to become an infrastructure supplier.
The question is no longer whether Ayar's idea is interesting. The question is whether it can become manufacturable infrastructure.
Section 6 · UCIeAn interoperable optical chiplet
Ayar announced what it describes as the world's first UCIe optical chiplet for AI scale-up architectures.[4] Ayar says TeraPHY delivers 8 Tbps of bandwidth and is powered by a 16-wavelength SuperNova light source, with optical connectivity scaling from millimeters to kilometers and UCIe enabling chiplet interoperability across vendors.[4] The performance numbers are Ayar claims. The strategic point is independent of those numbers. UCIe lowers the integration barrier for any AI ASIC, CPU, or accelerator team that wants to attach an optical I/O chiplet without building a private interface around it.
UCIe helps Ayar plug into chiplet systems. Optical I/O gives those systems reach beyond what copper can handle efficiently.
Section 7 · Alchip + TSMCInto real AI ASIC packaging
Ayar and Alchip announced a partnership to scale AI infrastructure with co-packaged optics, connecting Ayar's CPO technology with Alchip's advanced packaging and AI ASIC design expertise. The announcement explicitly references TSMC technologies including COUPE, TSMC-SoIC, and advanced process nodes, framing repeatable CPO integration as part of real AI ASIC packaging flows.[5] TSMC's COUPE research page describes the Compact Universal Photonic Engine as a silicon-photonics integration platform aimed at HPC and AI-class systems, with EIC and PIC integration as part of the platform.[9]
The reading is straightforward. Ayar is no longer only a GlobalFoundries Fotonix story. The Alchip partnership puts Ayar's optical I/O inside the broader TSMC advanced-packaging conversation that AI ASIC programs use today. The strategic upside is meaningful. So is the execution burden: optical chiplets now have to fit inside real packaging flows, with real customers, on real schedules.
If optical I/O is going to matter for hyperscaler ASICs, it has to fit inside real packaging flows, not only lab demonstrations.
Section 8 · WiwynnRack-scale deployment is the real test
Ayar and Wiwynn announced a partnership to bring CPO into rack-scale AI systems.[6] The joint solution integrates Ayar's TeraPHY optical engines and SuperNova remote light sources into Wiwynn's rack architecture, targeting 1,024 AI accelerators and beyond, with Ayar saying each accelerator can deliver more than 100 Tbps of optical connectivity. The announcement specifically calls out fiber management, thermal management, liquid cooling, manufacturability, external laser pluggables, and serviceability as the hard parts of bringing CPO into deployable racks.[6]
Can optics work in a demo is no longer the question. Can optics work inside a liquid-cooled, serviceable, manufacturable hyperscale rack is the real question.
Section 9 · Nvidia CPOValidated, but staged
Nvidia's silicon photonics page describes a co-packaged optics strategy in which CPO switches replace pluggable transceivers with silicon photonics integrated onto the same package as the switch ASIC, with claims of approximately 5x better power efficiency and approximately 10x higher network resiliency versus pluggable transceivers, positioned around Quantum-X InfiniBand Photonics and Spectrum-X Ethernet Photonics for AI factories.[7] Nvidia's developer blog frames the rollout as switch-first, with Quantum-X at approximately 115 Tb/s switching capacity and Spectrum-X at approximately 409.6 Tb/s switching capacity used as the entry points for CPO in AI networking.[8] Public reporting around the Nvidia GTC window noted explicitly that Nvidia is using CPO first in networking chips, with wider adoption inside GPU packages described as something that may take time.[13]
CPO is entering AI infrastructure through the network first. GPU-package optical I/O is the bigger prize, but also the harder reliability problem.
Section 10 · CompetitionThe market is moving, but Ayar is not alone
Optical I/O is no longer a science project. Lightmatter announced Passage M1000 with a claimed 114 Tbps optical bandwidth, positioning a photonic interconnect for next-generation XPUs and switches.[10] AMD acquired Enosemi to expand its co-packaged optics capability for next-generation AI systems.[11] Marvell announced it would acquire Celestial AI, whose Photonic Fabric targets package, system, and rack-level optical I/O, with Marvell explicitly framing the move around scale-up connectivity for next-generation data centers.[12] Read together, those moves describe a strategic AI infrastructure category, not a niche.
Ayar helped make the category real. Now it has to win inside a category every serious AI infrastructure company has noticed.
Section 11 · Proof pointsWhat Ayar must prove
- High-volume manufacturability across photonic and electronic dies.
- Micro-ring yield and tuning stability across temperature and process corners.
- Laser reliability and serviceability across rack-scale deployments.
- Fiber attach and fiber management at rack scale, not only at chip scale.
- Integration with UCIe, advanced packaging flows, and TSMC-class platforms.
- Liquid cooling compatibility inside dense AI racks.
- Production testing at scale, including burn-in and yield screening.
- Hyperscale deployment reliability across long device lifetimes.
- Cost competitiveness versus pluggables, copper, and active electrical cables.
- Interoperability with AI ASIC, GPU, switch, and memory architectures.
- Customer adoption beyond demos, partnerships, and reference designs.
The bottleneck has moved from physics to production.
Section 12 · Switch vs acceleratorTwo CPO problems, not one
| Category | Switch CPO | Accelerator-package optical I/O |
|---|---|---|
| Near-term adoption | Already being productised by Nvidia in AI networking | Still harder and less mainstream |
| Main benefit | Lower network power, fewer pluggables, higher resiliency | Direct scale-up communication between accelerators |
| Reliability challenge | Switch package serviceability and optics lifecycle | Failure risk near very expensive accelerators |
| Thermal challenge | Switch ASIC cooling plus optics | GPU / ASIC thermal density plus optics |
| System impact | Improves AI factory networking | Could redefine the accelerator socket and rack-scale memory and compute pool |
| Ayar relevance | TeraPHY can serve optical I/O needs around switches and ASICs | Bigger prize if optical I/O moves directly beside accelerators |
Section 13 · AI infrastructure impactWhy this matters
If optical I/O works at scale, it changes system architecture, not only cables. Larger scale-up domains become possible because reach is no longer copper-limited. Power per bit can drop, easing the data-center power envelope at fixed compute. Rack-to-rack communication can be tighter and more uniform. Composable memory and compute pools become more practical. AI ASIC architectures can be designed around optical I/O rather than around the SerDes pin count of a single package.
The long-term prize is not a better cable. It is a different computer.
Section 14 · EvidenceEvidence ledger
Section 15 · Risk registerRisks and limitations
This essay is an analysis of public disclosures and historical context. It is not investment advice. The honest risks against the read above run in several directions, and they are listed here so the argument can be stress-tested.
Section 16 · Bottom lineBottom line
The 2022 article was right that Ayar Labs was attacking the real AI infrastructure bottleneck: data movement. Optical I/O was never just about replacing copper with light. It was about changing the shape of systems so compute, memory, accelerators, and switches could communicate across racks with better power, reach, latency, and bandwidth density.
The 2026 update is that the market has validated the category. Nvidia is productising CPO switches, TSMC is developing COUPE, Alchip and Wiwynn are working with Ayar on ASIC and rack-scale integration, and major players like AMD, Marvell, Celestial AI, and Lightmatter are pushing optical I/O closer to compute.
But Ayar still has to prove the hardest part: production. CPO has to survive manufacturing yield, micro-ring tuning, laser reliability, fiber management, liquid cooling, testing, servicing, and hyperscale deployment.
Ayar was early to the right bottleneck. Now it has to prove co-packaged optics can ship as real AI infrastructure.
Section 17 · DefinitionsGlossary
Section 18 · MethodSources and method notes
The 2022 SemiAnalysis Ayar Labs piece is treated as historical context for the I/O wall framing, the in-package optical I/O thesis, the TeraPHY plus external-light architecture, the micro-ring modulator discussion, and the early HPE and Nvidia strategic interest. Ayar's product, bandwidth, and customer claims (8 Tbps TeraPHY, 16-wavelength SuperNova, 100+ Tbps per accelerator) are treated as Ayar's claims rather than as independently verified numbers.
The 2026 read is built from Ayar's Series D and Series E announcements, the UCIe optical chiplet announcement, the Alchip and Wiwynn partnership releases, Nvidia's silicon photonics page and CPO technical blog, TSMC's COUPE research page, and competitive announcements from Lightmatter, AMD (Enosemi), and Marvell (Celestial AI). Reuters coverage around Nvidia's GTC commentary is used carefully to anchor the staged-adoption argument. The structural arguments that Ayar was early to the right bottleneck, that the category is now validated but contested, and that the binding constraint is production rather than physics are independent analysis.
Footnotes · primary sources
- SemiAnalysis, “Ayar Labs | Co-packaged Optics Revolution | The Most Promising Hardware Startup With Wins At HPE And Nvidia?,” 2022 (PDF supplied by author). Historical anchor used in this essay for the in-package optical I/O thesis, the page 3 "case for in-package optical I/O" visual with package pin limits and rising off-chip I/O power, the page 4 distance/bandwidth/power penalty visual, the page 6 optical I/O redefining CPU socket framing, the page 9 TeraPHY chiplet visual, the page 11 optical I/O system architecture visual, the page 13 micro-ring modulator discussion, and the page 15 external laser and serviceability discussion. Strategic-investor and partner context (GlobalFoundries, Intel, HPE, Nvidia, Lockheed Martin, Applied Materials) is also drawn from this source.
- Ayar Labs, “Ayar Labs Closes $155M Series D to Address AI Infrastructure Bottleneck,” ayarlabs.com/…/series-d. Source for the approximately US$155M Series D in 2024, the approximately US$370M total funding figure, the valuation above US$1B, the strategic investor list including AMD Ventures, Intel Capital, and Nvidia, and the broader AI data-movement framing used in this essay.
- Ayar Labs, “Ayar Labs Closes $500M Series E, Accelerates Volume Production of Co-Packaged Optics,” ayarlabs.com/…/series-e. Source for the approximately US$500M Series E in 2026, the scaling of high-volume production and test capacity, the Hsinchu, Taiwan office expansion, the ecosystem partnership emphasis, and the production-ready CPO framing.
- Ayar Labs, “Ayar Labs Unveils World's First UCIe Optical Chiplet for AI Scale-up Architectures,” ayarlabs.com/…/ucie-optical-chiplet. Source for the approximately 8 Tbps TeraPHY optical I/O chiplet, the 16-wavelength SuperNova light source, UCIe interoperability, the millimeter-to-kilometer connectivity framing, and the AI scale-up architecture positioning.
- Ayar Labs, “Ayar Labs and Alchip to Scale AI Infrastructure with Co-Packaged Optics,” ayarlabs.com/…/ayar-alchip. Source for the AI ASIC integration framing, Alchip's advanced packaging and ASIC expertise, the cited TSMC COUPE, TSMC-SoIC, and advanced process node context, and the repeatable CPO integration into AI infrastructure used in this essay.
- Ayar Labs, “Ayar Labs and Wiwynn Partner to Bring Co-Packaged Optics to Rack-Scale AI Systems,” ayarlabs.com/…/ayar-wiwynn. Source for the rack-scale AI system framing, the 1,024 AI accelerators and beyond target, the more than 100 Tbps optical connectivity per accelerator claim, the integration of TeraPHY optical engines and SuperNova remote light sources, and the explicit fiber management, thermal management, liquid cooling, manufacturability, external laser pluggables, and serviceability emphasis.
- Nvidia, “Silicon Photonics,” nvidia.com/…/silicon-photonics. Source for Nvidia's CPO strategy framing, the approximately 5x power efficiency and approximately 10x network resiliency claims for CPO switches vs pluggable transceivers, and the Quantum-X InfiniBand Photonics and Spectrum-X Ethernet Photonics positioning used in this essay.
- Nvidia Developer Blog, “Scaling AI Factories with Co-Packaged Optics for Better Power Efficiency,” developer.nvidia.com/…/cpo-power-efficiency. Source for the switch-first CPO framing, the approximately 115 Tb/s Quantum-X switching capacity, the approximately 409.6 Tb/s Spectrum-X switching capacity, and the AI factory networking framing used in this essay.
- TSMC, “Compact Universal Photonic Engine (COUPE),” research.tsmc.com/…/coupe. Source for TSMC's silicon-photonics integration platform framing for HPC and AI-class systems and the EIC plus PIC integration context referenced in this essay.
- Lightmatter, “Lightmatter Unveils Passage M1000, the World's Fastest AI Interconnect,” lightmatter.co/…/passage-m1000. Source for the Passage M1000 framing, the claimed approximately 114 Tbps optical bandwidth, and the photonic interconnect positioning for next-generation XPUs and switches.
- Reuters, “AMD buys Enosemi to boost co-packaged optics offerings,” reuters.com/…/amd-enosemi-2025. Source for AMD's acquisition of Enosemi and the broader signal that optical I/O is becoming strategic to AI accelerator vendors.
- Marvell, “Marvell to Acquire Celestial AI, Accelerating Scale-Up Connectivity for Next-Generation Data Centers,” investor.marvell.com/…/marvell-celestial-ai. Source for the Celestial AI Photonic Fabric framing across package, system, and rack-level optical I/O, and the strategic rationale that copper must give way to optics within racks, systems, and packages.
- Reuters, “Nvidia CEO says power-saving optical chip tech will need to wait for wider use,” reuters.com/…/nvidia-cpo-cautious. Used carefully in this essay to support the staged-adoption argument, including the framing that Nvidia is using CPO first in networking chips and that wider adoption in mainstream GPUs may take time.