The Boring Back-End Boom.Original analysisNot investment advice
The semiconductor world talks about EUV, 2nm, HBM, and AI accelerators. But every chip still has to be assembled, bonded, packaged, tested, and shipped. The back-end is where wafers become products, and in 2026 it is becoming a strategic bottleneck.
In semiconductor writing, the front-end gets most of the glory. EUV. 2nm. Gate-all-around. HBM. CoWoS. AI accelerators. That is where the headlines go.
But every chip still has to leave the wafer. It has to be cut, attached, bonded, packaged, tested, inspected, shipped, and integrated into a system. That is the back-end. For years it looked less exciting than lithography, transistor scaling, or GPU architecture. It was the boring part of the semiconductor stack. That view is now wrong.
The back-end is becoming strategic.
The 2021 trailing-edge thesis was simple. Mature-node capacity was booming, and every extra wafer needed extra packaging. Kulicke & Soffa, a major supplier of wirebonding equipment, was positioned to benefit because trailing-edge semiconductors still relied heavily on wirebonding and conventional packaging flows.1 In 2026, the thesis is bigger. Mature nodes still run the real economy. AI makes advanced packaging more complex. China is expanding mature-node capacity. OSATs need more tools. Power modules need new interconnect methods. Memory needs higher-density packaging. The back-end sits in the middle of all of it.
The correct claim is not that trailing edge is better than leading edge. The correct claim is that the semiconductor boom is bifurcating. The leading edge is driven by AI accelerators, HBM, and advanced packaging. The trailing edge is driven by cars, power, industrial, IoT, and China localization. The back-end benefits from both because every chip still needs assembly, bonding, packaging, and test.
I. The 2021 thesis
In April 2021, Dylan Patel published a SemiAnalysis piece on Kulicke & Soffa, anchored in a simple observation. K&S produced wirebonding machines that were essential to trailing-edge semiconductor packaging. Mature-node capacity additions meant more packaging was needed, and ASE reported wirebonder delivery lead times of roughly 40 to 52 weeks during that cycle, signalling a capacity squeeze.1 The piece treated this as a window into a broader truth: the “boring” packaging layer can become a real bottleneck when wafers expand faster than back-end capacity.
I revisited that piece because the dynamic widened. The wirebonder constraint that defined 2021 is not the 2026 story. What 2021 actually called early was the strategic re-emergence of the back-end itself, across mature and advanced flows alike.
If mature-node wafer capacity expands, back-end packaging capacity must expand with it. Wirebonders become valuable when the “boring” packaging layer becomes a bottleneck.
II. The 2026 update
Six years later, the back-end is being pulled by two forces at once. Mature-node volume from cars, power electronics, analog, MEMS, sensors, MCUs, IoT, and industrial systems. And advanced packaging complexity from AI accelerators, HBM, chiplets, TCB, hybrid bonding, advanced substrates, and power modules. The K&S story is no longer about a wirebonder shortage. It is about interconnect diversity across very different end markets.
A wirebonder squeeze
- Driver · trailing-edge wafer boom.
- Bottleneck · wirebonders, lead times 40–52 weeks.1
- Map · K&S as the wirebonder beneficiary.
- Story · mature-node capacity catch-up.
Bifurcated boom, integrated back-end
- Drivers · cars + power + industrial + China + AI + HBM + chiplets.
- Bottlenecks · assembly + bonding + TCB + hybrid + power-module welding.
- Map · K&S as an interconnect-diversity platform.
- Story · back-end as a strategic layer of the AI stack.
III. Mature nodes still run the economy
The industry often talks as if older nodes are obsolete. They are not. Mature nodes power the parts of the world that are invisible until they fail: vehicles, factories, power systems, sensors, MCUs, MEMS, display drivers, and the analog plumbing of everything in between.
SEMI’s data backs this up. Global 200mm fab capacity is projected to grow roughly 14% from 2023 through 2026, reaching more than 7.7 million wafers per month, with 13 new 200mm volume fabs added across the period. Automotive and power semiconductor capacity is projected to grow about 34% over the same window.5
IV. China makes mature nodes strategic
Export controls have throttled China’s access to the most advanced semiconductor tools. They have not stopped the country from investing in chips. They have redirected the investment into mature nodes, packaging, and the supporting capacity stack.
Reuters has reported that China’s mature-node capacity, especially 22 to 40 nm chips used in cars, smartphones, and consumer electronics, is projected to rise from around 37% of global output in 2026 to roughly 42% by 2028, with AI demand increasing testing, packaging, and high-speed interconnect intensity along the way.9
Read that with the SEMI numbers and the picture sharpens. Mature nodes are no longer just older technology. They are industrial policy.
If China cannot dominate the bleeding edge quickly, it can still build massive capacity in mature chips, power devices, analog, MCUs, sensors, packaging, and test.
V. The back-end is not one thing
The back-end gets treated as a single step in chip diagrams. In practice, it is a stack with several decision points and very different flows depending on the end market.
Trailing edge: cars, analog, MCU, sensors
Leading edge: accelerators, HBM, chiplets
Power electronics: EV, grid, data center
VI. Wirebonding is still alive
Advanced packaging gets the AI headlines, but wirebonding has not gone away. Packaging is a stack, not a single technology, and the layers accumulate rather than replace each other. Reuters reporting on ASE makes the same point at the OSAT level: the company is positioning advanced packaging for AI as a meaningful growth driver, with revenue expectations stepping up sharply into 2026 while traditional packaging volume continues underneath it.8
Wirebonding stays massive. Advanced packaging grows above it. Both need more tools.
VII. AI makes the back-end more important
At first, trailing-edge packaging and AI seem unrelated. They are not. AI data centers need power modules, advanced packages, HBM integration, high-speed interconnect, more test, better thermal systems, memory packaging, substrates, and packaging capacity on top of everything the front-end produces.
SEMI’s equipment forecast puts the numbers next to that story. Global semiconductor equipment sales are projected to grow to $133B in 2025, $145B in 2026, and $156B in 2027. Assembly and packaging equipment is projected to grow about 19.6% in 2025, 9.2% in 2026, and 6.9% in 2027, with growth attributed to complex device architectures, advanced and heterogeneous packaging, and the performance requirements of AI and HBM semiconductors.6
AI made the front-end famous. The back-end is where every chip becomes a product.
VIII. K&S as the case study
Kulicke & Soffa is a useful lens because it sits inside the transition from mature packaging to interconnect diversity. K&S reported Q2 FY2026 revenue of $242.6M, up from Q1 and year over year, and guided Q3 FY2026 to about $310M ± $20M, citing stronger-than-expected demand across general semiconductor, memory, automotive, and industrial markets. The company also increased FY2026 capex to expand Thermo-Compression Bonding capacity for advanced packaging and memory workloads.2
That is not a single-product recovery story. It reads more like a platform broadening: the same company that owned the wirebonder squeeze in 2021 now ships TCB tools, power-module assembly systems, and memory interconnect solutions across multiple markets.
IX. From wirebonding to interconnect diversity
K&S frames the new portfolio explicitly. The ProMEM memory portfolio combines ball bonding, vertical wire, advanced TCB, and a future hybrid-bonding roadmap, with the company citing up to 20% higher throughput as a generational claim.3 ASTERION-TW is positioned as an ultrasonic terminal-welding platform for power-module manufacturing, with K&S highlighting copper-terminal welding up to 2 mm thick for renewable energy, transportation, data centers, and industrial power electronics.4
X. TSMC and the system-level story
The back-end story does not end at the OSAT. TSMC’s own roadmap treats packaging as a strategic layer of the semiconductor business, not an afterthought. The 2025 annual report frames AI/HPC demand as a primary driver of advanced packaging and 3DFabric investment, and the 2026 Technology Symposium briefings broaden the picture to include specialty technologies such as RF, embedded memory, power management, sensors, and ultra-low-power devices.1011
Semiconductor progress is no longer only a leading-edge logic story. It is a system story: advanced logic plus specialty nodes plus power plus sensors plus packaging plus test.
Quick terms
- Front-end
- Wafer fabrication where transistors and circuits are built on silicon.
- Back-end
- Assembly, packaging, bonding, and test steps after wafer fabrication.
- OSAT
- Outsourced semiconductor assembly and test provider.
- Wirebonding
- Connecting a die to package leads or substrate using thin wires.
- Wedge bonding
- Bonding method often used in power and specialty applications.
- Ball bonding
- Common high-volume wirebonding method for many mature packages.
- TCB
- Thermo-compression bonding for fine-pitch advanced packages.
- Hybrid bonding
- Direct bond approach for very dense die-to-die connections.
- SiP
- System-in-package: multiple components integrated in one package.
- 200 mm fab
- Older wafer size still widely used for mature-node devices.
- Mature node
- Older process technology used for analog, power, MCUs, sensors, and many non-leading-edge chips.
- Power module
- Package that handles high-current power conversion or control.
- Interconnect
- The physical connection path between chips, package, board, or system.
XI. What could break the thesis
A serious piece needs counterarguments. The case that the back-end has become strategic again has plausible failure modes.
- Mature-node overcapacity. Chinese expansion at 22–40 nm could swamp some end markets and squeeze pricing for the same chips the back-end depends on.
- Cyclicality. Wirebonder demand has historically swung sharply after shortage periods. Equipment orders can turn quickly.
- Concentration in advanced packaging. A small number of OSATs and foundries may capture most of the AI packaging growth.
- Long qualification cycles. TCB and hybrid bonding ramps can take years before they show up at scale.
- Lumpy AI packaging demand. Hyperscaler capex pauses propagate quickly into back-end equipment.
- China localisation. Domestic Chinese back-end equipment could displace non-Chinese suppliers in specific market segments.
- OSAT capex restraint. If end demand weakens, OSATs delay back-end equipment orders quickly.
- Power-module dependence on EVs. Power-module growth is closely tied to EVs, renewables, industrial, and data-center power demand.
- Substitution risk. Hybrid bonding could shift HBM and chiplet flows away from incremental tools toward different vendors.
- Test bottlenecks. The least glamorous part of the back-end could become the binding constraint, hurting other equipment categories.
The correct claim is not that every back-end company wins. The correct claim is that the back-end has become strategically important again.
XII. The boring layer became strategic
The semiconductor industry loves the frontier. 2 nm. EUV. HBM. AI accelerators. CoWoS. Nanosheets. But the real world still runs on mature chips. Cars need MCUs. Factories need sensors. Power systems need power devices. AI data centers need power modules. Servers need memory packages. Every wafer needs assembly and test.
The back-end used to look boring because it came after the exciting part. That was the wrong way to see it. The back-end is where chips become products.
That is why trailing edge is not dead. It is becoming strategic again.
1 Patel, D. (Apr 2021). Trailing Edge is Going Gangbusters ($KLIC). SemiAnalysis. Historical anchor for the mature-node and wirebonder thesis, including the ASE wirebonder lead-time figure of 40 to 52 weeks. Used as inspiration only. No content, structure, or charts reproduced.
2 Kulicke & Soffa (May 2026). Q2 FY2026 results. Q2 FY2026 revenue of $242.6M, Q3 FY2026 guidance of $310M ± $20M, demand across general semiconductor, memory, automotive, and industrial, and increased FY2026 capex to expand TCB capacity.
3 Kulicke & Soffa (Mar 2026). Expanded memory solutions portfolio. ProMEM portfolio combining ball bonding, vertical wire, advanced TCB, and a future hybrid-bonding roadmap, with up to 20% higher throughput as a generational claim.
4 Kulicke & Soffa (Mar 2026). ASTERION-TW ultrasonic terminal-welding system. Copper-terminal welding up to 2 mm thick for renewable energy, transportation, data centers, and industrial power electronics.
5 SEMI. Global 200 mm fabs to reach record-high capacity by 2026. 200 mm capacity growing about 14% from 2023 to 2026, more than 7.7 million wafers per month, 13 new volume fabs, automotive and power capacity up about 34%.
6 SEMI. Global Semiconductor Equipment Sales Projected to Reach a Record of $156 Billion in 2027. Total equipment $133B / $145B / $156B for 2025 / 2026 / 2027 and assembly and packaging equipment growth of 19.6% / 9.2% / 6.9% driven by complex device architectures, advanced and heterogeneous packaging, and AI/HBM requirements.
7 ASE. Q1 2026 results. Used as confirmatory context that wirebonding remains a meaningful portion of ATM operations alongside growing advanced packaging revenue. Cited via ASE’s public earnings communications.
8 Reuters (2026). ASE sees advanced packaging business doubling to $3.2 billion in 2026 and ASE expects strong demand to boost advanced chip packaging sales. Coverage of ASE’s advanced packaging trajectory for AI chips and the broader OSAT mix.
9 Reuters (Mar 2026). AI boom accelerates China’s chip industry growth. China mature-node output share rising from ~37% in 2026 to ~42% by 2028, including 22–40 nm chips for cars, smartphones, and consumer electronics, with AI driving testing, packaging, and high-speed interconnect pressure.
10 TSMC. 2025 Annual Report. AI/HPC demand and advanced packaging investment context, including 3DFabric framing.
11 TSMC. 2026 North America Technology Symposium. Advanced packaging, 3DFabric, and specialty technologies including RF, embedded memory, power management, sensors, and ultra-low-power devices.
- The AI Memory Wall. Companion essay on DRAM, HBM, packaging, and semicap as the new center of computing.
- The Dry Resist War. Patterning as a strategic process technology for AI-era chipmaking.
- The Density Illusion. Why Moore’s Law became a system problem.
- Nvidia Built the AI Factory Anyway. Vertical system integration as the new moat.
- The Modem-to-Antenna War. Apple unbundling Qualcomm’s modem-RF stack.
- MediaTek and the Fragmented Compute War. A neutral Taiwan fabless platform in a bifurcated compute world.
- The AI Field Manual. Reference layer for the AI stack: hardware, memory, models, agents, safety, economics.
This is Essay No. 018. The topics: intelligence, AI, systems, knowledge, and the questions underneath the questions everyone else is asking. If you read this far and disagreed with any part of it, write to me. I read everything.