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Essay No. 046 · AI Infrastructure · Melbourne, Australia

AI Infrastructure Applied Materials Advanced Packaging Panel-Level Packaging Topaz PVD CoWoS SoW-X TSMC Nvidia Blackwell HBM Glass Substrates Hybrid Bonding Fan-Out Packaging Chiplets Interposers

The Package Escaped the Wafer.Original analysisNot investment advice

How Applied Materials’ 600mm panel bet aged into the AI mega-package race.

Pugalenthi Magendran

May 2026 · Melbourne, Australia

12 min read

The 2021 Applied Materials article looked like a niche tool story: a PVD system modified for 600mm panels. In 2026, it reads like an early clue. AI compute is pushing packages beyond the old wafer-centric packaging model. CoWoS is expanding. SoW-X is coming. HBM counts are rising. Glass substrates are gaining attention. Panel-level fan-out is being tested for HPC and AI. The package is no longer just where the chip goes. The package is becoming the scaling surface.

In 2021, Applied Materials had a strange-sounding story.

A PVD tool. A panel. A substrate the size of a monitor. A packaging process borrowed from LCD panels, PCBs, and fan-out wafer-level packaging.

The uploaded SemiAnalysis article framed it clearly.¹ Applied was modifying a physical vapor deposition tool from its Tango Systems acquisition to support panel-level packaging on substrates around 600mm by 600mm. Applied’s own framing claimed this could come at less than half the normalised capital cost compared with wafer-level packaging.

At the time, that sounded niche.

In 2026, it looks like a preview.

AI packages are getting bigger. HBM counts are rising. Chiplets are multiplying. CoWoS is expanding. Substrate limits matter. Power delivery matters. Thermal-mechanical control matters. The package is becoming the system.

The old story was: Applied has a big panel PVD tool.

The better 2026 story is: AI compute is pushing advanced packaging beyond the wafer-centric mindset.

The package is becoming the scaling surface.

1. The 2021 thesis was really about area

The uploaded 2021 SemiAnalysis article is a useful historical anchor, not a script to copy. Its most important point was not the photo of the tool. It was the size of the substrate.¹

The story, in its own words, was that Applied had repurposed equipment from its Tango Systems acquisition for panel-level packaging, that the process drew on techniques used in LCD panels, PCB manufacturing, and fan-out wafer-level packaging, and that the tool was being aimed at substrates roughly 600mm by 600mm. Older details mentioned 670mm by 580mm formats. The article called the result “the size of your monitor.”

The tool could deposit layers as thin as 10µm. It could handle interconnect layers, low-resistance contacts, and conformal seed layers for etched or laser-drilled vias. It could support embedded-die substrate technologies like Intel’s EMIB and TSMC’s LSI. It could be used with organic or glass interposers. Applied’s broader Display Group capability stack added eBeam testing, SEM review and metrology, and focused ion beam defect analysis.¹

The deeper claim underneath all of that was simple. As advanced packages grow, the 300mm circular wafer becomes an awkward canvas for them. Package area was about to become a first-order bottleneck, and the company that figured out how to deposit, pattern, and inspect at panel scale would be selling tools into a different bottleneck than the one most of the industry was focused on.

The package was becoming too large to treat as an afterthought.

2. Why the wafer-centric model starts to strain

Wafers are circular. Most very large advanced packages are rectangular. The two shapes do not match well.

If you put a few large rectangular packages on a circular 300mm wafer, you waste a lot of the wafer at the edges. The bigger each package becomes, the worse the geometry gets. Panel-level packaging swaps the circular wafer for a much larger rectangular substrate. The trade is conceptually familiar from displays: rectangular glass utilises a flat surface more efficiently than a circular one when the things you are placing on it are themselves rectangular.

Applied’s own advanced-substrates page describes this in similar terms. It says that the 300mm wafer can constrain larger packages, that the industry is moving toward rectangular substrates as large as 600mm by 600mm, and that its Topaz PVD tools can deposit wiring on substrates at that scale, including double-sided deposition for some processes.²³ These are company claims, and they describe an industry direction more than a finished market.

The visual is easier than the prose.

Wafer vs panel · area utilisation

300mm wafer

~4 large packages fit cleanly. Edge area becomes harder to use as package size grows.

600mm panel

~16 same-size packages on a rectangular surface. Conceptual illustration, not yield.

Conceptual only. Real utilisation depends on bonding, lithography, panel-level yield, and edge-exclusion zones. Numbers shown are illustrative, not measured.

The larger the package, the worse the circular wafer starts to look.

3. Applied’s current roadmap still points there

The 2021 article was not a one-off. Applied’s public materials in 2026 still position panel-level packaging and large rectangular substrates as part of an “advanced substrates” roadmap, anchored by the Topaz PVD line.²³

The framing has shifted. The early story was a tool. The current story is closer to a market segment: substrates, wiring, redistribution layers, embedded-die structures, organic and glass options, and the deposition and inspection tools that go around them. Applied says the integration of more chiplets into a single package is what is driving the move toward larger and more sophisticated substrates. It is also the company’s own claim, which means you should read it as direction rather than market share.

The point is not that panel-level packaging has won. The point is that Applied is still drawing the same arrow it drew in 2021, only now it sits inside a more general story about the package as a scaling surface.

Topaz PVD · what it sits inside

STEP 01

PVD deposition

Thin metal films, including wiring layers, on large rectangular substrates.

STEP 02

Seed + contacts

Low-resistance contacts and conformal seed layers for etched or laser-drilled vias.

STEP 03

RDL + interposer

Redistribution layers, embedded-die bridges (EMIB / LSI), organic or glass interposers.

STEP 04

Panel format

Substrates up to ~600mm by 600mm; double-sided film deposition on some panels.

Source: Applied Materials Advanced Substrates and Topaz PVD pages. Process steps simplified for illustration; company claims rather than independent measurement.²³

If AI packages keep growing, the manufacturing canvas has to grow with them.

4. TSMC is proving the direction

The cleanest 2026 evidence that the industry sees the package as a scaling variable comes from TSMC’s own technology symposium.⁴

TSMC says it is in production with CoWoS at about 5.5 reticles of area. It says it is planning 14-reticle CoWoS by 2028, capable of integrating around 10 large compute dies and roughly 20 HBM stacks in one package. It expects a 40-reticle System-on-Wafer, SoW-X, by 2029. Its A14-to-A14 SoIC stacking is reported as offering about 1.8 times higher die-to-die I/O density than the N2-on-N2 SoIC generation. It also says its COUPE co-packaged optics on substrate begins production in 2026, with claimed roughly 2× power efficiency and roughly 10× latency reduction versus pluggable optics on the board.⁴

These are TSMC’s own claims, not independent benchmarks. Take the dates and numbers as direction, not as audited facts. But the direction is the point. CoWoS is not stopping at the current package size. Stacked-die density is increasing. Optics is moving from the board into the substrate. The package is being asked to carry the weight that used to live in the box around it.

TSMC packaging roadmap · reticle area

CoWoS · today (2026) ~5.5×

CoWoS · planned 2028 ~14×

SoW-X · expected 2029 ~40×

Bars proportional to TSMC’s stated reticle-area framing. Source: TSMC 2026 Technology Symposium.⁴ Numbers are TSMC company claims, not independent measurements.

The frontier of AI scaling has moved from the die to the package.

5. Nvidia shows why the packaging race matters

The clearest commercial pressure on advanced packaging shows up in Nvidia’s roadmap.

Reuters reported in January 2025 that Nvidia’s Blackwell generation uses TSMC’s CoWoS, and that Jensen Huang said Nvidia was moving largely toward the CoWoS-L variant for Blackwell, with CoWoS-S still in use for the Hopper line.⁵ The same reporting framed the constraint as not really about pulling back capacity but about expanding CoWoS-L capacity fast enough. Packaging, in other words, remained a bottleneck even after months of capacity build-out.

The reason is structural. An AI chip is not really a chip any more. It is a compute-and-memory system glued together with interposer, substrate, package, power delivery, and thermal path. Whether it works depends on the yield of the whole assembly, not just the GPU die. If any of those layers cannot scale, the system cannot scale.

Spotlight · Nvidia Blackwell

Reuters reports Blackwell uses TSMC CoWoS, and that Nvidia is moving largely toward CoWoS-L for Blackwell, with CoWoS-S still in use for Hopper. The framing was that the issue was not reducing capacity but increasing CoWoS-L capacity. Packaging remained a bottleneck even as capacity grew.⁵

If you want to picture the system, it looks something like this:

AI package anatomy

Cooling Cold plate / liquid loop / vapour chamber. Pulls heat out of the compute die.
Compute die GPU or accelerator logic die(s); sometimes multiple chiplets bonded together.
HBM stacks High-bandwidth memory stacks beside the logic die, connected through the interposer.
Interposer Silicon interposer or bridge (CoWoS-S, CoWoS-L, EMIB, LSI). Carries fine-pitch routing.
Substrate Organic build-up or glass substrate. Bridges fine interposer pitch to coarse board pitch.
Power / PCB Power-delivery network and board-level routing. Hundreds of amps into the package.

Simplified vertical view. Real packages mix variants of CoWoS, SoIC, EMIB, and substrate stack-ups, and may add co-packaged optics.

The bottleneck is shifting from “can we make the chip?” to “can we assemble the system?”

6. Why panel-level packaging is attractive

Once the package becomes the bottleneck, larger manufacturing formats stop being a curiosity and start being one of several reasonable answers.

Panel-level packaging tries to do for advanced packages what large-format glass did for displays. Larger rectangular substrates can fit more packages per pass, or one very large package per pass. Material costs spread across more area. Tooling does too, when yield works. ASE’s 2025 paper on 300mm panel-level fan-out describes the same direction in its own terms: better carrier utilisation, better material efficiency, higher throughput, and a scalability story aimed at high-performance computing and AI.⁷

You should treat that paper as ASE’s own framing, but the direction matches everything else in this essay. Bigger packages need a bigger factory floor, or at least a factory floor that does not waste so much of itself.

Why it’s attractive

Panel-level strengths

Larger continuous manufacturing area
Better utilisation for rectangular packages
Lower cost per package area when yield holds
Scaling path for very large fan-out packages
Compatible with organic or glass substrates
Process-flow parallels with PCB and display lines

Why it’s hard

Panel-level challenges

Warpage control across a large panel
Lithography precision over a big field
RDL and via uniformity across the panel
Panel handling, alignment, and thermal stress
Inspection and metrology at scale
Yield losses scale with area, not just with steps

Panel-level packaging is the attempt to give AI packages a bigger factory floor.

7. But the hard part is control

Bigger packages solve one problem and create another. Process control over a very large area is genuinely difficult. ASE’s own framing of panel-level fan-out lists the relevant challenges in plain terms: warpage control, complex process flows, patterning precision, solder-joint integrity, and reliability testing.⁷

The way to think about it is that yield losses, on a panel, do not just multiply per process step. They also stretch across area. If a defect rate is low enough that wafer-level packaging tolerates it, the same rate over a much larger surface can still take a panel out. Add in dimensional changes from temperature, panel bow, alignment drift, and the precision needed to bond dies and route nanometre-pitch interconnect, and the engineering becomes its own discipline.

None of this means panel-level packaging fails. It means it has to earn its way up the volume curve, and the bar is not lower than for wafer-level formats. It is in some ways higher, because the consequences of a mistake are bigger.

Panel-level risks · control problems that scale with area

Warpage

Thermal-mechanical stress bends large panels. Bonding and lithography both suffer when the panel is not flat.

Alignment

Stitching exposures and placing dies accurately across a big rectangular field is harder than across a small one.

Yield by area

Defect rate behaves like a tax on area. Even low rates become expensive at panel scale.

Bigger packages solve area pressure, but they multiply process-control pressure.

8. Glass substrates are part of the same story

Panel-level packaging is one answer to the package-as-scaling-surface problem. Glass substrates are another. They address different parts of the same pressure.

Intel’s own glass-substrate release frames the benefits in its own words.⁸ Glass offers better flatness than typical organic build-up substrates. It offers better thermal and mechanical stability under load. It enables higher interconnect density. Intel positions it as useful for data-intensive workloads such as AI, with commercial deployment aimed at the second half of this decade. Those are Intel claims, and they need to be read as direction rather than as audited timelines.

The connection to the panel-level story is that giant packages need a flatter, more stable canvas. Organic substrates begin to struggle as packages grow. Glass does not solve every problem — it brings its own — but it is being pushed by some of the same forces that make panel-level packaging interesting. Larger packages, denser routing, more chiplets, more memory, and more demanding power delivery all reward a substrate that does not move when temperature changes.

If the package becomes the system, the substrate becomes strategic.

9. Hybrid bonding is the vertical version of the same story

Panel-level packaging scales the package outward. Hybrid bonding scales it upward.

In a 2024 announcement, Applied introduced the Kinex die-to-wafer hybrid bonding system, developed with Besi.⁹ Hybrid bonding replaces solder bumps with direct copper-to-copper bonds between bonded surfaces. Applied positions it as a way to improve performance, power, and cost for advanced logic and memory chips.

The relationship to panel-level packaging is parallel, not competitive. The vocabulary of advanced packaging has grown a long list of related techniques that mostly answer the same question from different angles:

Advanced packaging approaches · same pressure, different axes

Approach	What it scales	Primary axis
Panel-level packaging	Package area on rectangular substrates	Horizontal area
Hybrid bonding	Direct die-to-die or die-to-wafer interconnect density	Vertical density
CoWoS (TSMC)	2.5D integration of compute + HBM on an interposer	2.5D fan-out
SoIC (TSMC)	3D die stacking with fine-pitch bonded interconnect	3D logic / memory
SoW-X (TSMC)	System-on-wafer at much larger reticle-area scale	Wafer-scale system
Glass substrates	Substrate flatness, stability, and routing density	Substrate quality

The honest description is that these are not competing winners. They are co-evolving answers. A future AI rack probably uses several of them in the same product.

Panel-level packaging scales package area. Hybrid bonding scales vertical density. AI will need both.

10. Applied is an equipment layer under the AI packaging transition

Applied’s 2026 financial framing reflects this shift. Reuters reported in May 2026 that Applied was guiding Q3 revenue around USD 8.95 billion, plus or minus USD 500 million, against Q2 revenue of USD 7.91 billion. Within that, Applied was expecting more than 30 percent growth in semiconductor equipment and more than 50 percent growth in packaging revenues for 2026, tied to AI and data-centre infrastructure demand.⁶

Those are company forecasts and Reuters reporting, not independent measurement. Forecasts can miss. But the composition matters more than the precise numbers. Applied has stopped being just a front-end wafer-fab equipment company in the way investors talked about it ten years ago. It sells process-control tools for the parts of AI scaling that happen after the transistor: PVD, CVD, etch, electroplating, metrology, inspection, hybrid bonding, advanced substrates, and panel-level processing.

Whether or not Applied’s specific packaging growth number lands on plan, the structural point holds. The post-transistor stack is where a growing share of the work, and a growing share of the bottleneck, now lives. Anyone selling tools and process control into that stack is exposed to the same trend that is pushing CoWoS, SoW-X, glass, and panel-level packaging at the same time.

Applied sells process-control tools for the parts of AI scaling that happen after the transistor.

11. Why this is bigger than Applied

The shape of the story is not really an Applied story. It is an AI infrastructure story.

AI compute is no longer limited only by transistor scaling. It is increasingly limited by how much logic, HBM, power delivery, cooling, and interconnect can be assembled into one package. The list of things that have to scale together has grown long.

Post-transistor scaling stack · everything that now has to scale

L9 · supplyFoundry, OSAT, substrate, HBM, and equipment capacity across the supply chain.

L8 · rackRack-level system architecture: NVLink, optics, power, cooling distribution.

L7 · opticsCo-packaged optics that move signal off the package without burning the power budget.

L6 · thermalsCold plates, liquid loops, and the thermal interface that limits how dense a package can get.

L5 · powerPower-delivery network. Hundreds of amps into a package at low voltage.

L4 · packageCoWoS, SoIC, EMIB, LSI, panel-level fan-out, glass substrates. The integration layer.

L3 · memoryHBM stack count, capacity, and bandwidth. Increasingly the binding constraint on AI throughput.

L2 · chipletChiplet count, die-to-die I/O density, and known-good die yield across the package.

L1 · transistorTransistor density and performance per watt. Still important; no longer alone.

The package is no longer just where the chip goes. The package is becoming the scaling surface.

12. The actual 2026 thesis

The correct claim is not that panel-level packaging will replace CoWoS. That framing is too crude. Different parts of the AI stack will want different things.

The correct claim is this:

Panel-level packaging is one answer to the same system-scale pressure that is pushing TSMC toward larger CoWoS and SoW-X. AI packages need more area, more memory, more chiplets, more power delivery, and more interconnect. The 2021 article about Applied’s 600mm panel PVD tool was right to focus on package area, because area is becoming a first-order scaling variable. In 2026, this future is no longer theoretical. TSMC is scaling CoWoS toward 14 reticles and SoW-X toward 40 reticles. Nvidia packaging remains a bottleneck. Applied’s advanced-substrate and packaging exposure is becoming more important. The package is escaping the wafer.

13. What could break the thesis?

Panel-level packaging has a serious bear case. The same forces that make larger formats attractive in theory make them difficult in volume.

Bear case

What could keep panels niche

Warpage control stays expensive at high volume
Panel lithography precision lags wafer steppers
Yield losses scale with panel area
Substrate handling and alignment remain hard
Defect inspection at panel scale stays immature
Thermal-mechanical stress limits very large designs
CoWoS and silicon interposer paths keep improving
Glass substrates slip out of their stated timelines
Customers prefer proven wafer-level formats
Panel-level packaging stays anchored in cost-sensitive or non-leading-edge packages

Bull case

What could break the bear case

AI packages keep growing faster than wafer formats can absorb
HBM stack counts and chiplet counts keep rising
Package area expands until rectangular formats are required
Glass substrates improve dimensional stability at scale
Applied’s Topaz PVD and inspection lines get higher attach
Panel-level fan-out becomes credible for HPC and AI
Packaging revenue grows faster than traditional equipment
CoWoS, SoW-X, panel fan-out, glass, and hybrid bonding coexist as different answers to the same pressure

Panel-level packaging may remain a better manufacturing idea than a near-term AI production reality.

14. What could break the bear case?

The bull case does not need panels to win everywhere. It only needs the AI package to keep growing.

If HBM stack counts go from 8 to 12 to 16 in the next few generations, if chiplet counts rise, if interposer area keeps expanding, if cooling and power delivery push package dimensions outward to give the thermal solution room, and if some AI products start looking less like chips and more like trays, then rectangular panel formats become a natural way to manufacture them. Not a replacement for CoWoS — an addition to it for the largest packages.

In that world, the rebalancing is gradual. CoWoS keeps doing the leading-edge integration. SoW-X handles the wafer-scale extreme. Glass substrates show up wherever organic build-ups run out. Panel-level fan-out picks up the long tail of large but not bleeding-edge packages. Hybrid bonding shows up wherever vertical density matters more than horizontal area. Applied sells equipment into more than one of those lines at once.

AI packages keep growing, and every millimetre of integration surface starts to matter.

15. What to watch

If you want to track whether the 2026 thesis is aging well, these are the signals that move first.

Watch list

TSMC 14-reticle CoWoS progress
TSMC SoW-X timeline updates
CoWoS-L capacity expansion
Nvidia Blackwell / Rubin packaging requirements
HBM stack count trends per AI accelerator
HBM supply constraints across DRAM makers
Applied Topaz PVD adoption news
Applied packaging revenue growth trajectory
Panel-level fan-out adoption in HPC and AI
ASE panel-level fan-out qualification milestones
Glass substrate commercialisation timing
Intel glass substrate progress updates
Organic substrate constraints at the high end
Warpage control improvements
Panel lithography and alignment improvements
Metrology and inspection tools for large panels
Hybrid bonding adoption beyond memory pilots
Co-packaged optics adoption in production AI
Power delivery and cooling changes inside AI packages
OSAT capacity additions in advanced packaging

16. The package escaped the wafer

The 2021 Applied Materials article looked like a niche tool story: a PVD system modified for 600mm panels.

In 2026, it reads like an early clue.

AI compute is pushing packages beyond the old wafer-centric packaging model. CoWoS is expanding. SoW-X is coming. HBM counts are rising. Glass substrates are gaining attention. Panel-level fan-out is being tested for HPC and AI.

The package is no longer just where the chip goes.

The package is becoming the scaling surface.

17. Glossary

Terms

Advanced packaging: Techniques for integrating multiple chips, memory, and interconnect into a single package.
PVD: Physical vapor deposition. A process for depositing thin metal or oxide films.
Panel-level packaging: Packaging process using large rectangular panels instead of circular wafers.
Fan-out packaging: Packaging method that redistributes a chip’s connections outward to a larger area.
RDL: Redistribution layer. Wiring layer that reroutes chip connections.
Interposer: Intermediate layer that connects dies and memory inside a package.
CoWoS: TSMC chip-on-wafer-on-substrate packaging technology.
CoWoS-L: CoWoS variant using local silicon interconnect or bridge-style structures.
CoWoS-S: CoWoS variant using a full silicon interposer.
SoIC: TSMC 3D stacking technology with bonded die-to-die interconnect.
SoW-X: TSMC System-on-Wafer roadmap technology at large reticle-area scale.
HBM: High-bandwidth memory. Stacked DRAM next to logic dies.
EMIB: Intel embedded multi-die interconnect bridge.
LSI: Local silicon interconnect, used inside advanced TSMC packaging.
Glass substrate: Substrate using glass for flatness, thermal stability, and routing density.
Hybrid bonding: Direct die bonding, often copper-to-copper, for dense vertical interconnect.
Reticle: Maximum exposure field size in lithography; used here as a package-size reference.
Warpage: Bending or deformation of a substrate or package under stress.
Metrology: Measurement and inspection processes used to control manufacturing.
OSAT: Outsourced semiconductor assembly and test. Companies that package and test chips.
COUPE: TSMC’s co-packaged optics solution that brings optics onto the substrate.

Sources

This essay treats the uploaded 2021 SemiAnalysis article as a cited historical anchor, in this essay’s own words. No SemiAnalysis text, charts, screenshots, or images are reproduced. No company logos are used. Specific numbers and claims are sourced from primary company materials and major news reporting. This is not investment advice.

This piece is original 2026 analysis. The 2021 SemiAnalysis article is used only as a historical anchor for the panel-level packaging framing, restated here in original wording. Specific numbers and claims are sourced from Applied Materials product and substrate pages, the TSMC 2026 Technology Symposium press release, Reuters reporting on Nvidia and on Applied Materials, ASE’s panel-level fan-out technology paper, the Intel glass-substrate release, and Applied’s 2024 Kinex hybrid-bonding announcement. No third-party charts, slides, or logos are reproduced. No specific Applied Materials, TSMC, Nvidia, Intel, ASE, Besi, ASML, or other security is being recommended.

¹ Uploaded SemiAnalysis PDF, Dylan Patel (SemiAnalysis), September 2021. Advanced Packaging The Size Of Your Monitor — Applied Materials, $AMAT, Modifies Panel PVD Tool For 60x60cm Fan Outs To Usher In A New Age Of Mega Packages. Used in this essay only as a historical anchor, framed in the essay’s own words. The article: described Applied modifying a physical vapor deposition tool tied to the Tango Systems acquisition for panel-level packaging on substrates around 600mm by 600mm, with older details mentioning 670mm by 580mm; described the result as “monitor scale”; framed the process as a convergence of LCD panel, PCB, and fan-out wafer-level packaging techniques; stated Applied’s claim of less than half normalised capital cost compared with wafer-level packaging; noted the tool could deposit layers as thin as 10µm; described interconnect layers, low-resistance contacts, and conformal seed layers for etched or laser-drilled vias; noted support for embedded-die substrate technologies such as Intel EMIB and TSMC LSI on organic and glass interposers; and referenced Applied’s Display Group capability stack including PVD/CVD deposition, eBeam testing, SEM review and metrology, and focused ion beam defect analysis. No SemiAnalysis text, charts, screenshots, or images from the PDF are reproduced.

² Applied Materials. Advanced substrates. Used for: company framing that 300mm wafer formats become constraining as packages grow, that the industry is moving toward rectangular substrates up to about 600mm by 600mm, that more chiplets per package drive larger and more sophisticated substrates, and that Applied positions advanced substrates as a roadmap rather than a single product. Treated as Applied’s own framing.

³ Applied Materials. Topaz PVD. Used for: company claims that Topaz supports panel-level packaging on substrates up to about 600mm by 600mm, that it deposits wiring and metal films on large advanced substrates, that some configurations support double-sided film deposition, and Applied’s framing of less than half normalised capital cost compared with wafer-level packaging where present. Treated as Applied’s own framing.

⁴ TSMC. 2026 Technology Symposium. Used for: TSMC’s own statements that it produces CoWoS at about 5.5 reticles today, plans 14-reticle CoWoS for 2028 with about 10 large compute dies and 20 HBM stacks per package, expects a 40-reticle SoW-X System-on-Wafer in 2029, that A14-to-A14 SoIC offers about 1.8× higher die-to-die I/O density than N2-on-N2 SoIC, and that COUPE on substrate enters production in 2026 with stated roughly 2× power efficiency and roughly 10× latency reduction versus pluggable optics. All numbers are TSMC company claims rather than independent measurement.

⁵ Reuters (January 2025). Nvidia CEO says its advanced packaging technology needs are changing. Used for: Blackwell using TSMC CoWoS, Jensen Huang’s description of Nvidia moving largely toward CoWoS-L for Blackwell, CoWoS-S still in use for Hopper, and the framing that the issue was not reducing capacity but increasing CoWoS-L capacity, with packaging remaining a bottleneck despite expansion.

⁶ Reuters (May 2026). Applied Materials sees quarterly revenue above estimates. Used for: Applied’s Q2 revenue of approximately USD 7.91 billion, Q3 revenue guidance of approximately USD 8.95 billion plus or minus USD 500 million, Applied’s expectation of more than 30 percent growth in semiconductor equipment for 2026, and more than 50 percent growth in packaging revenues for the year, tied to AI and data-centre demand. Treated as Reuters reporting and Applied’s own outlook.

⁷ ASE. 300mm Panel-Level Fan-Out Packaging Development. Used for: ASE’s own description of panel-level fan-out being explored for HPC and AI, with framing around carrier utilisation, material efficiency, throughput, and scalability, alongside challenges including warpage control, complex process flows, patterning precision, solder-joint integrity, and reliability testing. Treated as ASE’s own framing.

⁸ Intel. Intel unveils glass substrates for next-generation advanced packaging. Used for: Intel’s own framing of glass substrates offering better flatness, thermal and mechanical stability, and higher interconnect density than organic build-up substrates, with commercial deployment aimed at the second half of this decade and framing around data-intensive AI workloads. Treated as Intel’s own framing.

⁹ Applied Materials (2024). Applied Materials unveils next-gen chipmaking products, including Kinex hybrid bonding. Used for: Applied’s introduction of the Kinex die-to-wafer hybrid bonding system, partnership with Besi, framing around direct copper-to-copper bonding, and stated benefits in performance, power, and cost for advanced logic and memory chips. Treated as company-released framing.