Apple M2 Was the Costly Transition Chip. M5 Shows Apple's Real AI Silicon Direction. M2 M3 M4 M5 A15 IP LPDDR5 Unified memory GPU Neural Accelerators TSMC 3nm Fusion Architecture Local AI
M2 widened the platform with more die area, LPDDR5, GPU and media capability. M5 shows where Apple Silicon was really going: neural acceleration inside the GPU, unified memory bandwidth, local AI, pro workflows, and advanced packaging.
- Historical context: what the 2022 M2 die-shot article got right
- M2 was a platform widening, not a CPU revolution
- The die-size story is the cost story
- The P-core and E-core evidence
- The GPU and media story was more meaningful
- LPDDR5 and unified memory were the real platform cost
- M3 was the real GPU architecture reset
- M4 made on-device AI unavoidable
- M5 reveals Apple's real AI silicon direction
- M5 Pro and M5 Max show the packaging and memory strategy
- TSMC is the hidden center of the story
- ASML matters indirectly, TSMC is the direct source
- The real Apple Silicon arc
- What Apple must prove now
- 2022 thesis vs 2026 reality
- Evidence ledger
- Risks and limitations
- Bottom line
- Glossary
- Sources and method notes
- In 2022, Apple marketed M2 as a broad upgrade: 20 billion transistors, 24GB LPDDR5 support, 100 GB/s memory bandwidth, 18% faster CPU, 35% faster GPU, and stronger media and Neural Engine capabilities.
- The die-shot analysis showed a more complicated story: M2 was largely A15-derived IP with a larger die, more GPU area, larger cache and system logic, LPDDR5 support, and a bigger memory controller.
- The article's key insight was cost: M2 moved from M1's 118.91 mm² die to an estimated scaled 155.25 mm² die, while LPDDR5 and memory-controller area increased platform cost.
- M3, M4 and M5 clarified Apple's actual direction: GPU architecture, media acceleration, on-device AI, unified memory bandwidth, and advanced packaging mattered more than one huge CPU IPC leap.
- M5 is the clearest signal: Apple moved neural acceleration into every GPU core and scaled unified memory bandwidth for local AI and pro workflows.
Section 1 · Historical frameWhat the 2022 M2 die-shot article got right
The 2022 SemiAnalysis and Locuza piece on M2 made a careful, almost contrarian argument.[1] M2 was not M1.5, but it also was not a fresh architectural leap. M2 was generally based on A15-era IP, just as M1 was broadly based on A14-era IP. M2 was larger and costlier than M1. The authors questioned Apple's published die-image scaling and Locuza rescaled M2 using comparable SRAM and PHY structures to estimate M2 at approximately 155.25 mm² versus M1 at approximately 118.91 mm², with Apple's presented die size implying approximately 141.7 mm². The CPU IP looked close to A15 Avalanche and Blizzard. CPU gains came mostly from clocks and modest IPC movement, while GPU, media, and memory improvements were more meaningful. The article also flagged no clear SRAM shrink from first-generation to second-generation N5 and a notable LPDDR5 memory controller and PHY area increase.[1]
- Apple's M2 marketing panel: 20B transistors, 24GB LPDDR5, 100 GB/s memory bandwidth, 18% faster CPU, 35% faster GPU, 40% faster Neural Engine, and high-performance media engine.
- M1, M2 and A15 die comparison with Locuza annotations.
- Apple chip specs table (A13, A14, A15, M1, M2) with die size and transistor density, including the scaled M2 estimate of ~155.25 mm².
- M1 Firestorm, A15 Avalanche, and M2 Avalanche-derived P-core comparison; M2 P-core estimated at ~2.76 mm².
- M1 / A15 / M2 E-core comparison and GPU core comparison.
- SLC comparison and memory controller / PHY comparison, including LPDDR5 area increase to ~14 mm² vs ~8.1 mm² for M1's LPDDR4X.
- Cost pressure from larger die plus more expensive LPDDR5-6400 vs LPDDR4X-4266.
M2 was not Apple flexing a huge CPU leap. It was Apple paying more silicon and memory cost to widen the platform.
Section 2 · Platform wideningNot a CPU revolution
M2's CPU story was modest compared with the GPU, memory, and media story.[1] M2's P-core was based on A15's Avalanche lineage with Mac-specific modifications. M2's E-core looked very close to A15's Blizzard E-core. The P-core uplift came mostly from clocks, not a large IPC jump. The GPU moved to more cores and more shared logic. The media engine and LPDDR5 support mattered more for real Mac workflows than raw CPU IPC. Apple did not spend the M2 die budget on a new CPU generation; it spent it on platform width.
Apple did not spend the M2 die budget on a new CPU generation. It spent it on platform width.
Section 3 · Die sizeThe cost story
The page 5 specs table puts the die-size story in numbers. M1 die size is reported at approximately 118.91 mm². The Locuza-rescaled M2 estimate is approximately 155.25 mm². Apple-presented M2 scaling implies approximately 141.7 mm². The rescaling uses identical SRAM cells and PHY structures, and the measurement has an error window because it relies on Apple-provided imagery.[1]
M2's performance story was modest. Its cost story was not.
Section 4 · CoresThe P-core and E-core evidence
The page 6 P-core comparison places M2's Avalanche-derived P-core alongside M1's Firestorm and A15's Avalanche. The M2 P-core is estimated at approximately 2.76 mm² in the visual and is larger than M1 and A15 P-core comparisons. The shared L2 cache grew from 12 MB to 16 MB. The page 8 E-core comparison argues the M2 E-core looks nearly identical to A15's Blizzard E-core, and page 9 says the E-core complex grew only modestly compared with the broader CPU complex.[1] The evidence points to continuity, not reinvention.
The CPU evidence points to continuity, not reinvention.
Section 5 · GPU and mediaThe more meaningful story
The page 9 GPU comparison shows M1, A15, and M2 GPU cores at similar size per core, but Apple increased the core count, raised GPU clocks, and added more GPU area. The larger media engine improved creative workflows. The article explicitly framed Apple M-series silicon as excellent for creative professionals and Adobe-style workflows.[1] M2 looked underwhelming if judged only by CPU uplift; it made more sense as a creator and bandwidth platform update.
M2 looked underwhelming if judged only by CPU uplift. It made more sense as a creator and bandwidth platform update.
Section 6 · MemoryLPDDR5 and unified memory cost
The page 11 SLC and memory-controller comparison reports that each 2 MB SLC data array looked generally the same size across M1, A15, and scaled M2, with no clear SRAM shrink from first-generation to second-generation N5. The memory controller and PHY area grew significantly to support LPDDR5-6400. The article estimates the 128-bit LPDDR5 bus at about 14 mm² versus about 8.1 mm² for M1's 128-bit LPDDR4X, and notes that LPDDR5-6400 was significantly more expensive than LPDDR4X-4266 at the time.[1] Apple paid silicon area and BOM cost for bandwidth. That spend looks different by 2026, when local AI and pro workflows put a real premium on memory bandwidth.
The memory system looked expensive in 2022. By 2026, memory bandwidth looked like the right place to spend.
Section 7 · M3The real GPU architecture reset
The M3 family announcement framed M3 around the biggest leap forward in graphics architecture for Apple Silicon, built on 3nm and introducing Dynamic Caching, hardware-accelerated ray tracing, and hardware-accelerated mesh shading, with Dynamic Caching allocating local memory in hardware in real time to improve GPU utilization.[2] M3 was the point where Apple's Mac silicon story shifted from CPU efficiency miracle to GPU, memory, and media architecture.
M3 was the point where Apple's Mac silicon story shifted from CPU efficiency miracle to GPU, memory and media architecture.
Section 8 · M4On-device AI became unavoidable
Apple introduced M4 on second-generation 3nm technology, with a Neural Engine capable of up to 38 trillion operations per second and a GPU built on M3's architecture with Dynamic Caching, hardware ray tracing, and mesh shading.[3] M4 Pro and M4 Max carried second-generation 3nm into Macs, with Apple framing the family around Apple Intelligence, on-device AI, and pro workflows.[4] Apple's AI strategy after M4 became platform-wide rather than NPU-only.
M4 made Apple's AI strategy obvious: accelerate the whole device, not just one NPU benchmark.
Section 9 · M5The real AI silicon direction
Apple's M5 announcement frames M5 as the next big leap in AI performance for Apple Silicon. M5 is built on third-generation 3nm, has a 10-core GPU with a Neural Accelerator in each GPU core, a 16-core Neural Engine, and unified memory bandwidth of approximately 153 GB/s. Apple claims over 4x peak GPU compute performance for AI versus M4 and up to 45% higher graphics performance versus M4, with explicit framing around local AI workloads including diffusion models and LLMs.[5]
M5 is Apple's answer to the AI PC: not a discrete accelerator card, but neural acceleration inside the GPU plus unified memory bandwidth.
Section 10 · M5 Pro and M5 MaxPackaging and bandwidth strategy
Apple's M5 Pro and M5 Max announcement describes a Fusion Architecture that connects two third-generation 3nm dies into a single SoC using advanced packaging, with M5 Pro supporting up to approximately 307 GB/s unified memory bandwidth and M5 Max supporting up to approximately 614 GB/s with up to 128 GB of unified memory. Apple links the memory bandwidth to complex scenes, massive datasets, and higher LLM token generation.[6] The technical specs page is the source of truth for exact configurations.[7]
Apple's pro-chip strategy is becoming packaging plus bandwidth plus local AI.
Section 11 · TSMCThe hidden center
Apple's M-series roadmap is tightly coupled to TSMC's process cadence. TSMC's 3nm family includes N3, N3E, and N3P, positioned around improved power, performance, and density, with Fab 18 as the main 3nm production facility.[8] TSMC's smartphone-platform material also frames N3P as part of the broader 3nm cadence supporting mobile and HPC products.[9] Apple's M3, M4, and M5 progression should be framed as Apple architecture riding TSMC node cadence, with Apple as an early premium customer.
Apple Silicon is Apple design riding TSMC's node cadence better than almost anyone else.
Section 12 · ASMLIndirectly relevant
ASML matters because EUV enables the advanced nodes Apple uses through TSMC. But the direct evidence for Apple Silicon is Apple's product announcements and TSMC's process roadmap. This essay does not pivot into ASML lithography. The cleaner foundry lens is TSMC process cadence and Apple's ability to be an early premium customer on each new node.
ASML makes the machines. TSMC turns the machines into nodes. Apple turns those nodes into products.
Section 13 · The arcThe real Apple Silicon arc
Section 14 · Proof pointsWhat Apple must prove now
- Can GPU Neural Accelerators become broadly useful through Metal and Core ML?
- Can developers easily target Neural Engine, GPU, and CPU without fragmentation?
- Can unified memory bandwidth remain a practical advantage for local LLMs and diffusion models?
- Can Apple scale memory capacity without destroying product margins?
- Can Fusion Architecture scale beyond Pro / Max without thermal and cost problems?
- Can Apple keep riding TSMC node cadence as advanced nodes become more expensive?
- Can Apple Intelligence make local AI acceleration valuable enough for ordinary users?
- Can Apple maintain battery life while adding more AI and GPU compute?
- Can Apple's local AI story compete with cloud AI where model size matters more than device efficiency?
Apple's next silicon challenge is not only faster chips. It is making local AI useful enough that the hardware matters.
Section 15 · Then and now2022 thesis vs 2026 reality
| 2022 M2 observation | 2026 interpretation | Lesson |
|---|---|---|
| M2 used A15-derived IP | M2 was a transition chip, not a fresh architectural leap | Apple was pacing Mac silicon with mobile IP reuse |
| M2 die looked larger and costlier | Later chips used more advanced nodes and packaging to justify cost | Silicon area must buy platform capability |
| CPU uplift looked modest | Apple's bigger gains moved to GPU, media, memory, and AI | CPU is no longer the whole story |
| LPDDR5 controller was expensive | Unified memory bandwidth became central to local AI and pro workflows | Bandwidth was the right long-term bet |
| No clear SRAM shrink on N5 family | Memory hierarchy became harder and more important | Scaling is uneven even for Apple |
| M2 felt awkward | M3, M4, and M5 clarified the roadmap | M2 was the bridge, not the destination |
Section 16 · EvidenceEvidence ledger
Section 17 · Risk registerRisks and limitations
This essay is an analysis of public disclosures and historical context. It is not investment advice. The honest risks against the read above run in several directions.
Section 18 · Bottom lineBottom line
The 2022 article was right that M2 was not Apple's major architectural leap. It was a costly transition chip: larger die, A15-derived CPU IP, more GPU area, larger caches, LPDDR5 support, and higher memory-controller cost.
But the 2026 update is that M2 was only the awkward middle step. M3 reset Apple's GPU architecture on 3nm. M4 pushed stronger on-device AI. M5 moved neural acceleration into every GPU core and scaled unified memory bandwidth for local LLMs, diffusion models, graphics, and pro workflows.
Apple's real silicon direction is not just faster CPU cores. It is GPU-driven AI, unified memory bandwidth, media acceleration, and advanced packaging riding TSMC's process cadence.
M2 widened the platform. M5 shows where Apple Silicon was going.
Section 19 · DefinitionsGlossary
Section 20 · MethodSources and method notes
The 2022 SemiAnalysis and Locuza M2 die-shot analysis is treated as historical context for the M2 platform widening argument, the page 5 die-size table (with the noted measurement caveats), the pages 6-9 P-core / E-core / GPU comparisons, and the pages 11-12 SLC, memory controller, and cost discussion. Apple's M3, M4, M5, and M5 Pro / Max claims are treated as Apple claims rather than independently validated figures.
The 2026 read is built primarily from Apple's M3 family announcement, the M4 announcement, the M4 Pro / M4 Max announcement, the M5 announcement, the M5 Pro / M5 Max announcement, and the M5 Pro / M5 Max technical specs page, plus TSMC's 3nm and advanced-smartphone-technology pages. ASML is referenced only as indirect context. The structural arguments that M2 was a transition chip rather than a failure, that M3 was the GPU architecture reset, that M4 made on-device AI platform-wide, and that M5 plus Fusion Architecture defines Apple's local-AI direction are independent analysis.
Footnotes · primary sources
- SemiAnalysis and Locuza, “Apple M2 Die Shot and Architecture Analysis — Big Cost Increase And A15 Based IP,” 2022 (PDF supplied by author). Historical anchor used in this essay for the page 2 Apple M2 marketing claims (20B transistors, 24GB LPDDR5, 100 GB/s memory bandwidth, 18% faster CPU, 35% faster GPU, 40% faster Neural Engine), the page 4 M1 / M2 / A15 die comparison, the page 5 Apple chip specs table with M1 at ~118.91 mm² and scaled M2 at ~155.25 mm² vs Apple-presented ~141.7 mm², the page 6 Firestorm / Avalanche / M2 P-core comparison and ~2.76 mm² P-core estimate, the pages 8-9 E-core and GPU core comparisons, the page 11 SLC and memory controller / PHY discussion (LPDDR5 bus area ~14 mm² vs ~8.1 mm² LPDDR4X), and the page 12 cost-pressure discussion (LPDDR5-6400 vs LPDDR4X-4266).
- Apple, “Apple Unveils M3, M3 Pro, and M3 Max, the Most Advanced Chips for a Personal Computer,” apple.com/…/m3-m3-pro-m3-max. Source for M3 on 3nm, Dynamic Caching, hardware-accelerated ray tracing, hardware-accelerated mesh shading, the “biggest leap forward in Apple Silicon graphics” framing, faster CPU / efficiency cores, and improved media engine.
- Apple, “Apple Introduces M4 Chip,” apple.com/…/m4-chip. Source for M4 on second-generation 3nm, the Neural Engine up to 38 trillion operations per second, the M3-derived GPU architecture with Dynamic Caching, hardware ray tracing and mesh shading, and the on-device AI positioning.
- Apple, “Apple Introduces M4 Pro and M4 Max,” apple.com/…/m4-pro-m4-max. Source for the Mac family transition to second-generation 3nm, the M4 Pro and M4 Max platform scaling, the Apple Intelligence and pro workflow positioning, and the unified memory framing.
- Apple, “Apple Unleashes M5, the Next Big Leap in AI Performance for Apple Silicon,” apple.com/…/m5. Source for M5 on third-generation 3nm, the Neural Accelerator in each GPU core, the over 4x peak GPU compute for AI vs M4, the up to 45% higher graphics performance vs M4, the 153 GB/s unified memory bandwidth, the 16-core Neural Engine, and the local LLM and diffusion model framing.
- Apple, “Apple Debuts M5 Pro and M5 Max to Supercharge the Most Demanding Pro Workflows,” apple.com/…/m5-pro-m5-max. Source for Fusion Architecture connecting two third-generation 3nm dies into one SoC, advanced packaging, M5 Pro up to ~307 GB/s unified memory bandwidth, M5 Max up to ~614 GB/s unified memory bandwidth and up to 128 GB unified memory, and the LLM token generation, massive dataset, and complex scene framing.
- Apple, “M5 Pro / M5 Max Technical Specifications,” support.apple.com/…/m5-pro-m5-max-tech-specs. Source for exact M5 Pro / M5 Max configurations, memory bandwidth options, and unified memory capacity details used in this essay.
- TSMC, “3nm Technology,” tsmc.com/…/3nm. Source for the TSMC 3nm family including N3, N3E, and N3P, the 3nm performance / power / density positioning, and the Fab 18 as main 3nm production facility context.
- TSMC, “Advanced Smartphone Technology Platform,” tsmc.com/…/advanced-smartphone-technology. Source for the broader TSMC platform context covering smartphone, HPC, and mobile process cadence, used in this essay only as supporting framing for Apple's TSMC dependence.