Essay No. 056 · Foundry Roadmaps & AI Manufacturing
The Node Race Became a System Race. Original analysis Not investment advice
In 2021, TSMC's 3nm delay looked like an opening for Intel and Samsung. In 2026, the verdict is clearer: the race did not end, but it became much harder to read.
The winner is not simply the company with the smallest marketing number. The winner is the company that can turn a node into a high-yield, high-volume, package-integrated platform for AI-scale systems.
For years, the semiconductor node race looked easy to understand from the outside.
A smaller number meant a better node. A better node meant faster chips, lower power, and better economics. Apple took the first wave. Other customers followed. The foundry with the best node won the best chips. That world is not gone, but it is much harder to read now.
The 2021 TSMC N3 issue was not only a delay. It showed that starting production and shipping meaningful wafers were no longer the same event. Cycle time, EUV exposure count, wafer cost, yield, design readiness, and customer risk all became central to whether a node turned into a real business.
Starting production is not the same as shipping meaningful wafers.
Section 01 What the 2021 N3 article got right
The 2021 SemiAnalysis piece on N3 is the historical anchor for this essay[1]. TSMC had said N3 high-volume manufacturing would begin in the second half of 2022. SemiAnalysis argued meaningful N3 shipments and revenue would not show up until Q1 2023 because of long cycle time, putting the gap between N5 and N3 at roughly 2.5 years and making N3 too late for the 2022 iPhone cycle.
The piece also documented why the delay was structural rather than incidental. TSMC had publicly described 3 nm as technically complicated. SemiAnalysis estimated N3 could require roughly 30 to 35 EUV exposures per wafer, with EUV throughput acting as a ceiling on monthly wafer output. It estimated N3 wafer costs were higher than N5 because of process complexity and equipment cost. And it framed the N3E nodelet as an improvement to manufacturing window, yield, defect density, and transistor performance rather than a clean shrink. Looking forward, it framed 2025 as a battle between TSMC 2 nm, Samsung 2 nm, and Intel 20A[1].
- N3 shipments and revenue framed as arriving in Q1 2023, ~2.5 years after N5.
- N3 described as too late for Apple's 2022 iPhone cycle.
- TSMC called 3 nm technically complicated.
- Estimated N3 EUV exposures at roughly 30 to 35 per wafer.
- N3 cycle time was rising due to process complexity.
- N3 wafer cost estimated above N5.
- N3E framed as manufacturing-window, yield, defect-density, and transistor-performance improvement.
- 2025 framed as a TSMC 2 nm vs Samsung 2 nm vs Intel 20A battle.
That article was directionally right about where the leading edge was going. Node transitions were becoming slower, more expensive, and harder to execute. It was specific about 20A as Intel's flagship in 2025. By 2026, that specific bet looks like the part of the framing that aged the worst, for reasons the rest of this essay will get into.
Section 02 N3 was not a disaster, but it was a warning
N3 became a real TSMC platform. But it became a family, not a single clean transition. TSMC's own page says it moved 3 nm FinFET into high-volume production in 2022, then introduced N3E and N3P for better power, performance, and density, with continuing extensions through N3X for HPC, N3C for cost-effective designs, and N3A for automotive[2].
That is the part of the story that the 2021 framing did not fully anticipate. The advanced node is no longer one node to rule them all. It is a portfolio of tuned platforms, each with different cost, power, performance, and customer profiles. A foundry's leading-edge story is now a family tree, not a single milestone.
Section 03 TSMC N2, the execution machine continued
The clean update from TSMC is that N2 started volume production in Q4 2025 as planned. N2 uses first-generation nanosheet transistor technology and is positioned as a full-node improvement in performance and power consumption[2]. The 2021 slowdown did not mean TSMC lost the race. But the nature of the race changed.
TSMC's lead became less about saying 2 nm first and more about turning 2 nm into a usable, high-volume customer platform. That requires standard-cell libraries, IP, EDA support, packaging integration, and customer tape-outs at scale, on top of the underlying transistor work. The marketing number is a precondition, not a victory.
Section 04 Intel 20A was not the real battlefield, 18A was
The 2021 framing put Intel 20A on the 2025 battle map. By 2026, Intel's practical story had moved one node further. Intel's own newsroom confirms that Panther Lake is the first client SoC built on Intel 18A, that Panther Lake was in production in 2025, and that Clearwater Forest is Intel's first 18A-based server processor expected in the first half of 2026. Intel 18A uses RibbonFET gate-all-around transistors and PowerVia backside power delivery, and Intel describes it as delivering up to 15% better performance per watt and 30% improved chip density versus Intel 3, with Foveros providing the packaging path for multi-chiplet integration[3].
That bundle is important. Intel 18A is the first commercial node to combine two major scaling levers at once: GAA transistors and backside power. The internal-product story is real. The harder question is whether Intel can also turn 18A into a trusted external-foundry process with sustained volume execution, which is a different test from getting Panther Lake out the door.
Section 05 Samsung pushed GAA early, but execution is the question
Samsung was early to GAA at 3 nm and has continued to push 2 nm GAA into AI accelerator design wins. Samsung announced a turnkey semiconductor solution for Preferred Networks using its 2 nm GAA process and advanced 2.5D packaging, explicitly aimed at AI accelerator chips[4]. That is a concrete customer-side data point for the 2 nm GAA platform.
The honest version of the Samsung story is that the GAA push matters and the customer logo matters, but advanced foundry is decided by yield, utilization, customer breadth, and cost per good die, not by architecture announcements alone. Samsung is a serious contender. Calling Samsung the 2 nm leader requires evidence that this essay's source pack does not, by itself, deliver.
Section 06 Why the race became harder to read
Node names no longer capture the whole race. A modern leading-edge platform is the sum of a long list of variables, and the foundries do not all weight those variables the same way.
A node is no longer just a transistor. It is a complete manufacturing platform.
Section 07 Backside power became a new scaling lever
Traditional chips deliver both power and signals through the front side of the wafer. As interconnects get denser, those two roles fight for the same routing tracks, which limits both performance and density. Backside power delivery moves power routing to the back side of the wafer. That frees front-side routing for signal density and improves voltage delivery to the transistors.
On TSMC's side, A16 integrates nanosheet transistors with the Super Power Rail backside power delivery scheme. TSMC says A16 improves logic density and performance, with 8 to 10% speed improvement at the same voltage or 15 to 20% power reduction at the same speed compared with N2P, and lists the N3 family extensions N3E, N3P, N3X, N3C, and N3A on the same family of pages[5]. On Intel's side, 18A uses PowerVia for backside power delivery alongside RibbonFET[3]. The next scaling lever is not only smaller transistors. It is better power delivery.
Section 08 AI changed the roadmap
AI chips are large, they use advanced logic, they want as much HBM as possible, and they live inside increasingly elaborate packages. That pushes foundries to solve system-level bottlenecks, not just transistor scaling. The TSMC 2026 Technology Symposium described 5.5-reticle CoWoS in production today and 14-reticle CoWoS planned by 2028, with the larger version expected to integrate around 10 large compute dies and 20 HBM stacks in a single package, alongside roadmap notes on A13, A14, A12, N2U, SoIC, and co-packaged optics[6].
That set of roadmap items is not, by itself, an EUV throughput claim or a transistor density claim. It is the system pressure that the node race now has to accommodate. AI made advanced packaging part of the node race.
Section 09 ASML and EUV are the hidden gate
The foundry race depends on ASML execution beneath it. ASML's 2026 AGM material says AI compute demand has outpaced Moore's Law alone, and that the future of compute scaling is not just smaller transistors but a combination of 2D scaling and 3D integration, including packaging, hybrid bonding, and chiplet architectures[7]. The Q4 FY2025 deck adds detail on EUV productivity, High-NA readiness, and the AI-driven capacity picture[8].
The practical implication is that even the best foundry node roadmap is limited by the manufacturing equipment stack beneath it. More EUV exposures per wafer at the leading edge means lithography throughput and tool availability matter, alongside source power, uptime, and High-NA insertion timing. Capacity is not free.
Section 10 The new definition of winning
Winning the node race in 2026 means a long list of things at once. High yield. Stable cycle time. Customer design success. Competitive power and performance. Usable standard-cell libraries. SRAM and analog support. Packaging integration. HBM attach. Enough capacity to matter at AI scale. Cost per good die that holds up against the alternatives. And roadmap trust that survives a multi-year customer commitment.
A press release can announce a node. Only manufacturing execution can make it real.
Transistor architecture
EUV productivity
Backside power
Design ecosystem
Yield learning
Advanced packaging
HBM integration
Capacity & customer trust
Section 11 2021 prediction vs 2026 reality
The 2021 article was directionally right about the slowing transition and the structural cost increase. It was specific about names, and that specificity is where the framing has to be corrected.
N3 delay; 2025 as a 2 nm three-way fight
- N3 slower and more expensive than N5.
- Node transitions stretching.
- Intel and Samsung have a window.
- 2025 framed as TSMC 2 nm vs Samsung 2 nm vs Intel 20A.
- Race read through transistor pitch and EUV exposures.
Family of nodes; system-level race
- N3 became a family: N3E, N3P, N3X, N3C, N3A.
- TSMC N2 entered volume production in Q4 2025.
- Intel's real story shifted to 18A, with RibbonFET and PowerVia.
- Samsung pushed 2 nm GAA and AI accelerator wins; yield and breadth still the test.
- Race now includes backside power, EUV productivity, CoWoS, HBM, SoIC, customer trust.
TSMC N5 begins customer shipments
N5 anchors leading-edge customer designs and sets the baseline for the N3 transition gap[1].
SemiAnalysis flags N3 timing and complexity
Long cycle time, EUV exposure count, and N3E framing make the transition look slower and more expensive[1].
TSMC N3 high-volume production begins
3 nm FinFET enters HVM. N3E, N3P, N3X, N3C, N3A then extend the family over time[2].
N3 revenue and broader shipments arrive
Meaningful customer revenue from N3, roughly the 2.5-year cadence after N5 that SemiAnalysis predicted[1].
TSMC N2 enters volume production
N2 starts volume production in Q4 2025 on first-generation nanosheet transistors[2].
Intel Panther Lake on 18A enters production
Panther Lake becomes the first client SoC built on Intel 18A with RibbonFET and PowerVia[3].
Samsung pushes 2 nm GAA for AI and mobile
Samsung announces turnkey 2 nm GAA solutions with 2.5D packaging, including a Preferred Networks AI accelerator engagement[4].
TSMC targets 14-reticle CoWoS and broader A-series roadmap
14-reticle CoWoS with ~10 compute dies and 20 HBM stacks; A13, A12, N2U, SoIC, and CPO extensions on the roadmap[6].
Section 12 Risks and limits
The argument above leans heavily on company materials, supplemented by the historical SemiAnalysis frame and ASML's macro context. It is worth being explicit about where the case can break.
TSMC, Intel, and Samsung official claims are company claims and should be treated as guidance, not verified benchmarks.
Production start is not the same as broad customer shipments at high volume.
Node names across foundries are not directly comparable on transistor pitch or density.
Performance, power, and density claims depend on test conditions, libraries, and design choices.
Yield data is usually not public, which limits how much of the race outsiders can actually see.
Packaging capacity and wafer capacity are different bottlenecks and can move independently.
Intel 18A can be real and still face external-customer adoption challenges; that is the foundry-trust test.
Samsung can be technically advanced and still face yield, customer breadth, or cost-per-good-die hurdles.
TSMC can lead and still face cost, cycle time, capacity, and geopolitical risk simultaneously.
AI demand can soften or reshape, changing the timing and economics of every roadmap in this essay.
The point is not that one company has already won forever. The point is that the scoreboard changed.
Section 13 Final verdict
The 2021 N3 delay was not a one-off stumble. It was an early sign that leading-edge foundry competition was becoming more complex. TSMC still looks like the best execution machine on the public record, with N2 in volume production and the N3 family extended into a portfolio. Intel's comeback depends on whether 18A becomes a trusted external-foundry process, not just a working internal node. Samsung's GAA push matters, and the AI accelerator engagements are real signals, but execution and breadth remain the test.
AI made the whole race more urgent and broadened the surface where the race is decided. The node race now includes process, power, packaging, yield, EUV productivity, HBM, customer trust, and capacity at AI scale.
The node race did not end. It became a system race.
Section 14 Evidence ledger and source notes
| Source | Claim | Why it matters |
|---|---|---|
| SemiAnalysis (2021) | N3 shipments pushed to Q1 2023; ~2.5-year N5-to-N3 gap; ~30-35 EUV exposures per wafer; rising cycle time and cost. | Anchors the historical case that node transitions were getting structurally harder. |
| TSMC N2 page | N2 in volume production from Q4 2025 on first-generation nanosheets; N3 family extends through N3E, N3P, N3X, N3C, N3A. | Confirms that the leading edge is a portfolio, not a single milestone. |
| Intel Newsroom | Panther Lake first 18A client SoC in production 2025; Clearwater Forest first 18A server processor in H1 2026; 18A uses RibbonFET and PowerVia; +15% perf/W and +30% density vs Intel 3. | Documents the GAA-plus-backside-power milestone and the real Intel battlefield. |
| Samsung newsroom | Turnkey 2 nm GAA plus 2.5D package solution for Preferred Networks AI accelerators. | Concrete 2 nm GAA customer signal; not by itself a yield or breadth claim. |
| TSMC A16 page | A16 combines nanosheet transistors with Super Power Rail backside power; 8-10% speed at iso-V or 15-20% power at iso-speed vs N2P. | Shows how TSMC frames the next scaling lever as power delivery. |
| TSMC 2026 Symposium | 5.5-reticle CoWoS today; 14-reticle by 2028 with ~10 compute dies and 20 HBM stacks; A13, A12, N2U, SoIC, CPO extensions. | Demonstrates that the node race now embeds packaging and HBM integration. |
| ASML 2026 AGM | AI compute demand outpaces Moore's Law alone; future scaling combines 2D scaling and 3D integration. | Macro frame that justifies the system-race reading. |
| ASML Q4 FY2025 | EUV productivity, High-NA readiness, and AI-driven capacity context. | Reminds that lithography productivity is the hidden gate on every node. |
Footnotes & sources
- SemiAnalysis, “TSMC 3nm Wafer Shipments Pushed Into Q1 2023, 2.5 Years After N5 | TSMC 2nm, Samsung 2nm, And Intel 20A Battle It Out In 2025,” 2021 (PDF supplied by author). Source for the Q1 2023 N3 shipment timing, the ~2.5-year N5-to-N3 gap, the Apple-2022-cycle observation, the ~30 to 35 EUV exposures per wafer estimate, the N3E manufacturing-window framing, and the 2025 TSMC 2 nm vs Samsung 2 nm vs Intel 20A battle line.
- TSMC, “2 nm Technology,” tsmc.com/dedicatedFoundry/technology/logic/l_2nm. Source for N2 Q4 2025 volume production on first-generation nanosheets, the N2 full-node improvement framing, and the broader 3 nm family extensions.
- Intel Newsroom, “Intel Unveils Panther Lake Architecture — First AI PC Platform Built on 18A,” newsroom.intel.com. Source for Panther Lake as the first 18A client SoC in production in 2025, Clearwater Forest as the first 18A server CPU expected in H1 2026, the RibbonFET and PowerVia framing, the up to 15% perf/W and 30% density improvement vs Intel 3 claim, and the Foveros multi-chiplet integration framing.
- Samsung Newsroom, “Samsung Electronics to Provide Turnkey Semiconductor Solutions with 2nm GAA Process and 2.5D Package to Preferred Networks,” news.samsung.com. Source for the 2 nm GAA plus 2.5D turnkey solution targeting AI accelerator chips. Treated here as a concrete customer signal, not as a 2 nm leadership claim.
- TSMC, “A16 Technology,” tsmc.com/dedicatedFoundry/technology/logic/l_A16. Source for the A16 nanosheet plus Super Power Rail backside power framing, the 8-10% speed at iso-voltage or 15-20% power at iso-speed comparison vs N2P, and the N3 family list including N3E, N3P, N3X, N3C, and N3A.
- TSMC, “TSMC 2026 Technology Symposium,” pr.tsmc.com/english/news/3302. Source for the 5.5-reticle CoWoS in production today and the 14-reticle CoWoS plan by 2028 with around 10 compute dies and 20 HBM stacks, as well as the A13, A14, A12, N2U, SoIC, and co-packaged optics roadmap notes used as system-pressure context.
- ASML, 2026 AGM Presentation, ourbrand.asml.com/…/2026_-AGM-_presentation.pdf. Source for the statement that AI compute demand has outpaced Moore's Law alone and that future scaling combines 2D scaling with 3D integration.
- ASML, Q4 FY2025 Press Conference Presentation, ourbrand.asml.com/…/Q4FY2025. Source for EUV productivity, High-NA readiness, and AI-driven capacity context used to frame ASML's hidden-gate role on the node race.