The EUV Throughput Bottleneck. Original analysis Not investment advice

EUV lithography is one of the strangest machines humanity has ever industrialized.

A system the size of a bus fires powerful lasers at microscopic molten tin droplets, creates plasma, collects a tiny fraction of the emitted 13.5 nm light, reflects it through ultra-precise mirrors, and prints patterns on wafers at nanometer scale. The whole choreography repeats roughly fifty thousand times per second when the tool is producing wafers^[2].

The old question was: can EUV print the pattern. That is a resolved question. The new question is: can EUV print enough patterns, cheaply enough, reliably enough, at AI scale.

Photons are expensive.

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Section 01 What the 2021 article got right

The 2021 SemiAnalysis piece on ASML and Lyncean is the historical anchor for this essay^[1]. It framed EUV light-source power as a constraining factor for leading-edge wafer manufacturing, explained the tin-droplet-plus-CO2-laser mechanism that ASML's existing scanners use, and warned that this approach would not scale forever, especially once High-NA EUV started consuming even more photons per wafer pass.

The article carried a few concrete claims. TSMC's N3 family was estimated to need roughly 20 to 25 EUV exposures per wafer. A fab equipped with a small number of EUV machines would face hard monthly wafer ceilings if source power and uptime did not improve. And it introduced Lyncean's accelerator-style compact synchrotron concept as a potential alternative source architecture, with a system footprint of roughly 5 m by 12 m and demonstrated source levels in the 2 kW range, while also cautioning that collection issues meant this was unlikely to replace ASML's existing method any time soon^[1].

Read carefully, that piece was right about the bottleneck and cautious about the replacement architecture. That caution aged well.

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Section 02 How ASML actually makes EUV light

The actual ASML process is more elegant than it sounds. EUV uses a 13.5 nm wavelength. ASML generates it by ejecting molten tin droplets, hitting each droplet first with a shaping pre-pulse that flattens or distorts it, then hitting it with a stronger main pulse that vaporizes it into plasma. The plasma emits EUV light. Specialized mirrors collect and guide the light into the scanner's optics. The sequence repeats around fifty thousand times per second according to ASML's own explainer^[2].

That is the easy version. The hard version is that EUV light is absorbed by ordinary air, so the whole system operates inside vacuum chambers. Conventional refractive lenses do not work at 13.5 nm, so the system has to use reflective optics with multilayer coatings tuned to that wavelength. Only a small fraction of the photons generated at the source actually reaches the wafer surface. Source power, collector lifetime, optics quality, resist sensitivity, uptime, and contamination all feed into how productive a scanner can be in production.

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Section 03 Why photons determine capacity

Every EUV exposure has to deliver enough photons into the resist to print a clean image. If photon flux is low, the scanner has to expose longer to reach the required dose. Longer exposure means lower wafers per hour. Lower wafers per hour means higher cost per wafer. Higher cost per wafer means more expensive leading-edge chips, on top of an already expensive process.

That is why source power is not a physics curiosity. It is an economics input. A scanner that costs north of $250 million only earns its place in a fab if it processes enough wafers reliably to amortize that cost. Productivity improvements that come from better source power, faster stages, higher uptime, or better resist sensitivity can be as commercially important as new tool shipments.

Photon supply becomes wafer supply.

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Section 04 Lyncean was the interesting wrong answer

The 2021 article introduced Lyncean because it offered a genuinely different source architecture. Instead of laser-produced plasma from tin droplets, Lyncean's concept used an accelerator-style compact synchrotron. Electrons are accelerated, circulated, and wiggled with magnets so that they emit photons in the EUV range. The article described the system at roughly 5 m by 12 m, with claimed demonstrations at 2 kW source power, and argued that the architecture could in principle scale much further^[1].

The challenge was never only generating EUV photons. The challenge was collecting and delivering useful EUV power into a lithography scanner, with the uptime, integration, serviceability, contamination control, and economics that a high-volume production tool requires. By 2026, the industry had not pivoted to Lyncean as the high-volume EUV solution. Lyncean was useful because it made the bottleneck obvious. It was not the route the industry ultimately took, which is a different claim from saying it failed.

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Section 05 ASML improved the existing machine

The clearest evidence for the productivity story is on ASML's own slides. ASML's 2026 AGM material says EUV capacity has grown more than 30%, and that the TWINSCAN NXE:3800E achieved a record throughput of 230 wafers per hour for high-volume manufacturing^[3]. The Q4 FY2025 press conference deck adds that ASML had shipped eight High-NA systems by the end of 2025, with six already in operation, and that the first second-generation High-NA system, TWINSCAN EXE:5200B, was running at a customer site and meeting full specs^[4].

ASML also flagged that High-NA EUV is being matured for high-volume manufacturing requirements by the end of 2026, with customer insertion expected in the 2027 to 2028 window^[4]. The solution to the 2021 bottleneck did not come from replacing ASML. It came from ASML making the existing tin-droplet architecture more productive year after year.

The solution was not replacing ASML. It was ASML making the existing architecture more productive.

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Section 06 The 1,000W update

The most striking number in the 2026 cycle came from a Reuters report on ASML's source-power roadmap. ASML demonstrated a path from roughly 600 W to 1,000 W of EUV source power, with a target of around 330 wafers per hour by the end of the decade, still based on tin droplets. The improvements involve a higher droplet rate and a refined laser-pulse sequence, rather than a fundamentally new light-source architecture^[5].

That is not a small improvement. Moving from roughly 220 to around 330 wafers per hour is a major productivity shift. It does not, in itself, increase yield per wafer. It increases the number of wafers a given scanner can process in a given time. In a capacity-constrained AI market, that distinction is the difference between extending a fab and building one.

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Section 07 Why High-NA makes throughput harder

High-NA EUV is often described as the next obvious step, but the engineering reality is more complicated. NA stands for numerical aperture. Higher NA improves resolution, and High-NA EUV can in some layers reduce the number of multi-patterning steps needed at the most aggressive features. That is the resolution win.

The cost is everywhere else. High-NA systems are more expensive, harder to integrate, and bring new constraints around field size, mask design, resist behavior, overlay, stitching, process integration, and tool productivity. ASML's Q4 FY2025 framing says High-NA is being matured for high-volume manufacturing requirements by the end of 2026, with customer insertion expected in 2027 to 2028, which is the right framing for a tool family that is still earning its way into mainstream production^[4]. Reuters has reported on early indications of High-NA readiness in the same window^[6]. High-NA helps with resolution. The industry still has to win the productivity and integration battle on top of it.

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Section 08 Why AI makes this urgent

AI chips are large, they use advanced logic nodes, and advanced logic nodes require EUV. AI accelerators also drive demand for more HBM, more advanced packaging, and more leading-edge capacity at the same time. Every wafers-per-hour improvement on every EUV scanner in the world feeds directly into how much AI silicon the industry can make.

TSMC's process roadmap puts numbers around the pressure. The 3 nm family extends across N3, N3E, N3P and other variants^[7]. N2 entered volume production in Q4 2025 using first-generation nanosheet transistor technology^[8]. On the packaging side, TSMC's 2026 Technology Symposium described 5.5-reticle CoWoS in production and 14-reticle CoWoS planned by 2028, with the larger version expected to integrate around 10 large compute dies and 20 HBM stacks in a single package^[9]. That packaging line is not itself an EUV throughput claim, but it is the demand signal that decides how much EUV the industry actually needs.

AI does not only need more chips. It needs more EUV-exposed wafers.

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Section 09 EUV as an economic bottleneck

The economics of leading-edge lithography are unforgiving. EUV scanners are extraordinarily expensive. Mask sets are expensive. Resist, pellicles, optics, uptime, source modules, and field service all cost real money. Throughput drives cost per wafer because fixed tool costs are spread across whatever output the tool can produce. Higher throughput on the same installed base improves the unit economics of every leading-edge wafer the industry ships.

This is why productivity improvements at the source can be as strategically important as new scanner shipments. A fleet that already exists, processing 30% more wafers per hour, is in many ways equivalent to extending the fleet, with much less capital and a much shorter lead time. At the leading edge, lithography is not just a process step. It is a capacity gate.

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Section 10 What people got wrong in 2021

The weak interpretation of the 2021 article was something like this: ASML's EUV method is hitting a wall, so a new source architecture will replace it. That reading collapsed two different claims, one about the bottleneck and one about the replacement candidate, into a single prediction.

The better interpretation is that EUV source power was a real bottleneck, but the incumbent architecture had more room to improve than outsiders expected. ASML and its supply chain kept pushing source power, collector performance, uptime, scanner productivity, stage speed, overlay, serviceability, and High-NA readiness, all on the same tin-droplet base. The bottleneck did not vanish. It became a productivity roadmap.

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Section 11 Risks and limits

The argument above relies on a mix of company materials, Reuters reporting, and TSMC roadmap statements. It is worth being explicit about where the case can break.

The point is not that ASML solved EUV forever. The point is that EUV has become a productivity race.

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Section 12 Final verdict

The 2021 article was right that EUV source power was a structural bottleneck. It was wrong only if it is read as predicting that an outside source architecture would become the high-volume answer in the near term. By 2026, ASML had extended the existing tin-droplet architecture. NXE:3800E reached 230 wafers per hour. High-NA tools shipped and ran at customer sites. ASML demonstrated a path to 1,000 W source power and around 330 wafers per hour by the end of the decade. The bottleneck did not disappear. It became the productivity race inside leading-edge manufacturing.

The bottleneck did not vanish. It became a productivity roadmap.

AI does not only need more chips. It needs more EUV-exposed wafers, more uptime per scanner, more photons per second, and lower cost per wafer at the leading edge. That is the test for the rest of the decade.

EUV is no longer just about resolution. In the AI era, EUV is about throughput, uptime, photons, and cost per wafer.

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Section 13 Evidence ledger and source notes