The Bonding Step Became the AI Packaging Bottleneck. Original analysis Not investment advice

Most people talk about advanced packaging as if the important part is the package name.

CoWoS, SoIC, Foveros, EMIB, HBM, and hybrid bonding all sound like distinct technologies. Underneath those acronyms is a more basic question: how do you physically attach one die to another without destroying yield? Dies have to be placed, aligned, and bonded without warpage, voids, contamination, tilt, or thermal damage. As AI packages become larger and more expensive, that physical step becomes strategic.

The AI chip is not only designed in EDA and printed in a fab. It is won or lost at the bond.

---

Section 01 What the 2022 TCB article got right

The 2022 SemiAnalysis piece on thermocompression bonding is the historical anchor for this essay^[1]. It framed TCB as an evolution of standard flip chip, noted that TCB was already used in HBM and across most Intel packaging technologies, and called Intel's deep TCB investment unusual because TCB was slower and more expensive than standard flip chip. The piece walked through the standard flip-chip flow on page 2, the failure modes from CTE mismatch on page 4 (substrate warpage, die warpage, chip gap variation, die tilt), and the reliability and bond defects on page 6.

The TCB section introduced the tool as a head that places individual dies, applies pressure, and heats the bond from the top, with the bonding profile on page 9 plotting temperature, bond force, and bond head position. The economics were laid out cleanly on page 10: TCB at roughly 500 to 1,000 dies per hour and about $1.25M per tool, versus flip chip at roughly 3,000 to 10,000 dies per hour and about $450K per tool. The piece also documented Intel's mixed-pitch packaging for Sapphire Rapids and Foveros Omni on pages 12 to 13, with EMIB at 55-micron pitch and other die-to-package connections around 100 microns, and explained why HBM uses TCB on pages 15 to 16 because the DRAM dies in the stack are extremely thin^[1].

The 2022 article was right because it judged TCB by process control, not only by throughput. The 2026 update has to ask the harder question: what has AI done to that tradeoff.

---

Section 02 Flip chip is fast, but heat creates risk

Standard flip chip is mature, cheap, and high-throughput. It works well for many packages. But batch reflow heats the entire assembly. Different materials expand at different rates. That coefficient-of-thermal-expansion mismatch produces substrate warpage, die warpage, chip gap variation, die tilt, voids, contamination, and reliability failures under thermal cycling^[1].

Flip chip is not bad. It is just not enough for every AI-era package, where bigger dies, thinner dies, and higher package values raise the cost of any of those defects.

---

Section 03 TCB trades throughput for control

Thermocompression bonding places and bonds dies one at a time. It applies local heat, pressure, and alignment. Heat comes from the top, so the substrate is not stressed in the same way as in batch reflow. Pressure reduces gap variation and die tilt. Fluxless or vibration-assisted processes can help reduce oxidation and contamination. The bonding profile shows temperature, force, and bond head position evolving together over a few seconds per die^[1].

TCB is slower, but the package is now too valuable to bond carelessly.

TCB is slower and more expensive. It is also more precise. In high-value packages, the slow precise step costs less than the yield loss from the fast one.

---

Section 04 Intel's bet looked strange until AI made packages expensive

Intel invested deeply in TCB and owned hundreds of tools, using TCB even in places where standard flip chip might have been acceptable^[1]. The case for that spend was reliability, high power, high margin, and packaging flexibility. The mixed-pitch reality of Sapphire Rapids and Foveros Omni made TCB more useful because the bond head can handle different connections in the same package without redesigning the entire assembly process.

Intel was paying for optionality and reliability before the rest of the AI market fully priced them. That looked expensive at the time. In 2026, with AI accelerators selling for tens of thousands of dollars per package and HBM stacks taller than ever, it looks closer to insurance.

---

Section 05 HBM made TCB strategic

HBM is stacked DRAM. The dies are extremely thin. The stack needs precise vertical alignment and reliable microbump connections, and as HBM stacks grow taller, bonding gets harder. The 2022 piece described an HBM stack with DRAM dies, microbumps, TSVs, underfill, and a logic die, and pointed to SK hynix's 12-stack HBM3 direction with DRAM dies thinned to roughly 30 microns. It said TCB was mandatory for HBM stacks at the time, while the industry looked toward hybrid bonding for the next generation^[1].

HBM is not only a memory story. It is a bonding story. The reason HBM scales is that the bond between layers behaves predictably enough to support the wide bus that gives HBM its bandwidth advantage.

---

Section 06 AI changed the economics of bonding

In cheap packages, bonding cost matters most. In expensive AI packages, yield and reliability matter more. If a final AI accelerator package is worth tens of thousands of dollars and contains multiple compute dies and HBM stacks, a bonding defect is catastrophic. That changes the tradeoff between cheap high-throughput bonding and slower high-control bonding. When the package becomes expensive enough, process control becomes cheaper than yield loss.

---

Section 07 ASMPT shows the TCB demand signal

ASMPT's 2025 annual results confirm the tool-market side of the thesis. Advanced packaging revenue reached US$532.1M in 2025, up 30.2% year over year, with TCB revenue growing about 146% year over year. ASMPT raised its estimated TCB total addressable market from about US$760M in 2025 to US$1.6B in 2028, with demand driven by AI investment, advanced logic, and HBM applications^[2].

ASMPT also disclosed additional orders for 15 chip-to-substrate TCB tools for cutting-edge AI computing chips from what it described as a major OSAT partner of a leading foundry^[3]. That is the tool-market version of the 2022 thesis. The TCB tool market is the quiet signal under the AI packaging boom.

The hidden bottleneck is not only CoWoS capacity. It is bonding capacity, bonding accuracy and bonding yield.

---

Section 08 K&S and Besi show this is not a one-tool story

Kulicke & Soffa expanded TCB production capacity and expected its TCB business to grow approximately 70% sequentially in fiscal 2026, positioning TCB demand across both logic and memory, with fluxless TCB capability and low-resistance copper-to-copper interconnect framing in its memory-solutions update^[4]. Besi's 2024 Investor Day framed AI, chiplets, 2.5D and 3D packaging, hybrid bonding, TCB, and advanced flip-chip interconnects as part of the same advanced logic and memory opportunity, with assembly processes varying by pitch and application^[5]. Besi's Q4 25 and full-year 2025 results, treated here as company reporting, point in the same direction across hybrid bonding and TC adoption in AI-relevant programs^[6].

The bonding bottleneck is becoming an equipment ecosystem, not a single company story. That is what you would expect for a process step that has just been promoted from back-end commodity to AI infrastructure layer.

---

Section 09 TCB vs hybrid bonding is the wrong debate

TCB and hybrid bonding sit at different points on the cost-density curve. TCB uses microbumps and combines pressure with local heat. Hybrid bonding removes solder microbumps entirely and bonds copper to copper directly, enabling much tighter pitch, better bandwidth, and lower power. The catch is that hybrid bonding is much harder to manufacture at scale. TCB is the bridge between today's microbump-based AI packaging and tomorrow's hybrid-bonded 3D systems.

TCB is the bridge between today's microbump-based AI packaging and tomorrow's hybrid-bonded 3D systems.

---

Section 10 HBM4 shows the nuance

Semiconductor Engineering reported that HBM4 was widely expected to require hybrid bonding for 16-high stacks, but a JEDEC height-limit change gave the industry more room to continue with microbump-based approaches. The reporting frames hybrid bonding as postponed, not cancelled, with HBM5 a stronger candidate for broad hybrid bonding adoption^[10].

Hybrid bonding is postponed in some places, not cancelled.

The industry is not moving in a straight line. Microbumps and TCB can be extended further than the early hybrid-bonding-everywhere predictions implied. Hybrid bonding will arrive where the density and power benefits justify the manufacturing difficulty, layer by layer, product by product.

---

Section 11 Intel Foveros Direct shows the density frontier

Intel's Foveros Direct 3D technology brief describes direct copper-to-copper hybrid bonding that eliminates traditional solder microbumps, achieves sub-10 micron pitch, and provides up to 10x finer interconnect density than conventional microbump technology, with Intel positioning it for AI accelerators, HPC, and advanced mobile^[7].

This is where the bonding roadmap is going. TCB gives better control over microbumps. Hybrid bonding removes microbumps for denser vertical integration. The bonding roadmap is a density roadmap.

---

Section 12 TSMC SoIC shows the foundry route

TSMC's SoIC page describes ultra-high-density vertical stacking with heterogeneous integration of known-good dies, starting from sub-10 micron bond pitch, with shorter die-to-die connections, higher bandwidth, better power integrity, and lower power consumption, and integration with CoWoS and InFO^[8]. The 2026 Technology Symposium adds that TSMC is producing 5.5-reticle CoWoS, plans 14-reticle CoWoS in 2028 (around 10 large compute dies and 20 HBM stacks), and targets A14-to-A14 SoIC for 2029 at 1.8x higher die-to-die IO density than N2-on-N2 SoIC^[9].

SoIC is the foundry version of the same trend: dense bonding becomes part of system-level scaling. The larger the AI package becomes, the more the bond determines the system.

---

Section 13 What people get wrong

Three common misreadings deserve direct correction. First, "TCB is just a slower version of flip chip" misses the control argument. TCB is a different technology because it solves a different problem: process control for high-value, high-reliability packages, not throughput. Second, "Hybrid bonding replaces TCB" ignores the cost-density curve. TCB and hybrid bonding coexist because they solve different cost-density problems and will continue to share AI-package real estate for years. Third, "The bottleneck is only CoWoS capacity" understates the supply chain. CoWoS capacity matters, but so do bonding tools, HBM stacking, underfill, substrates, assembly, test, and yield.

The hidden bottleneck is the physical act of joining the AI computer together.

---

Section 14 Risks and limits

The bonding-as-bottleneck argument blends 2022 history, tool-company filings, and foundry roadmaps. It is worth being explicit about where the case can break.

The point is not that one bonding technology wins everything. The point is that AI packaging made bonding strategic.

---

Section 15 Final verdict

The 2022 article was right. Intel's TCB bet looked strange when judged by cost and throughput. AI changed the economics. Packages became larger. HBM stacks became thinner. Chiplets became more common. Mixed-pitch systems became more valuable. Final packages became too expensive to lose casually at the bonding step.

TCB remains the workhorse for many microbump-based high-reliability packages. Hybrid bonding is the next density frontier. The tool ecosystem now matters because the physical act of bonding dies together has become one of the real constraints on AI hardware.

The AI chip is not only designed in EDA and printed in a fab. It is won or lost at the bond.

---

Section 16 Evidence ledger and source notes