Essay No. 076  ·  AI Infrastructure / CXL / Memory Fabric
Marvell CXL Memory Pooling AI Infrastructure Composable Servers Structera Tanzanite Data Centers HBM KV Cache

Marvell's Tanzanite Bet Was Early. CXL Is Now Becoming the Memory Pooling Layer for AI Infrastructure. Marvell Tanzanite CXL Structera A Structera X Structera S XConn Memory pooling KV cache Composable AI servers

AI infrastructure is not only constrained by GPUs and HBM. It is also constrained by memory capacity, utilization, and flexibility. CXL is the attempt to turn stranded DRAM into a composable memory tier.

PM
PUGALENTHI MAGENDRAN
May 27, 2026  ·  Research memo  ·  Updating a 2022 Tanzanite / CXL thesis
16 MIN
Thesis
The 2022 Tanzanite article was right that CXL memory pooling would matter for composable servers. In 2026, the thesis is stronger because AI has made memory capacity, bandwidth, utilization, and KV-cache economics central infrastructure problems. Marvell has turned the idea into a serious portfolio with Structera A, Structera X, Structera S, Alaska P, XConn switching, and custom CXL silicon. But the realistic role of CXL is not to replace HBM. HBM remains the high-bandwidth memory tier for accelerators. CXL becomes the flexible memory tier around the system.
In this essay
  1. Historical context: what the 2022 Tanzanite article got right
  2. Why memory utilization matters
  3. CXL basics without the jargon
  4. The 2026 update: Marvell turned the thesis into a portfolio
  5. Why AI makes CXL more important
  6. Structera S is the rack-scale proof point
  7. XConn completes the switching angle
  8. CXL 4.0 shows the standard is still moving
  9. The latency trade-off still matters
  10. CXL is not replacing HBM
  11. What this means for AI inference
  12. Marvell's broader AI infrastructure strategy
  13. What Marvell must prove
  14. Evidence ledger
  15. Risks and limitations
  16. Bottom line
  17. Glossary
  18. Sources and method notes
Executive summary
  • In 2022, Marvell acquired Tanzanite to fill a CXL memory-pooling gap in its data-center silicon portfolio.
  • The old article argued that CXL would enable composable server architectures where compute, memory, storage, and accelerators are allocated around workload needs.
  • That thesis aged well because AI has made memory capacity, bandwidth, utilization, and KV-cache economics central infrastructure problems.
  • Marvell has now built a broader CXL portfolio: Structera A near-memory accelerators, Structera X memory-expansion controllers, Structera S CXL switches, Alaska P retimers, XConn switching, and custom CXL silicon.
  • The realistic role of CXL is not replacing HBM. It is becoming the flexible capacity and utilization tier around AI systems.

Section 1  ·  Historical frameWhat the 2022 Tanzanite article got right

The 2022 SemiAnalysis piece on Marvell's Tanzanite acquisition framed CXL as a standardized protocol for cache coherency and memory pooling, and treated Tanzanite as the missing memory-pooling piece in Marvell's data-center silicon portfolio after the earlier Cavium, Avera Semi, Inphi, and Innovium acquisitions.[1] The strategic argument was simple. Data centers are not homogeneous. Workloads need different ratios of CPU, memory, storage, accelerators, and networking. Fixed server configurations create waste because customers often pay for resources they do not fully use. DRAM is one of the most expensive components per server, so improving memory utilization matters. CXL was the protocol that would let memory be expanded and pooled rather than permanently fixed to one CPU or server.[1]

2022 PDF page references used in this essay
  • CXL Type 1, Type 2, and Type 3 devices: caching devices / accelerators, accelerators with memory, and memory buffers.
  • Micron-cited CXL TAM chart sketching a path from a small 2025 market toward a much larger 2030 opportunity.
  • Rack-scale CXL Type 3 memory-pooling concept.
  • Tanzanite memory-pooling demo with multiple host CPUs and Tanzanite memory devices over PCIe / CXL.
  • Latency penalty discussion, comparing pooled memory to CPU-to-CPU NUMA-like latency rather than local DRAM.
  • Single-host memory expansion contrasted with true memory pooling beyond one CPU host.

The future server is not a fixed box. It is a pool of compute, memory, storage, and accelerators composed around the workload.

Section 2  ·  UtilizationWhy memory utilization matters

Cloud infrastructure is not a uniform blob. Some workloads need lots of memory and few cores. Some need many cores and moderate memory. Some need accelerators but limited CPU memory. Some need temporary memory bursts. Fixed servers strand resources because the workload mix never matches the SKU mix exactly. Stranded DRAM is especially expensive because memory is a large fraction of server cost.[1]

Old model
Fixed box
CPU owns local DRAM. Memory is fixed when the server is built.
CXL model
Attached and pooled
Memory can be attached, expanded, and pooled as a resource rather than locked to one socket.
Composable model
Resource on demand
Workloads request the mix of compute, memory, storage, and accelerators they actually need.

CXL is not just a bandwidth story. It is a utilization story.

Section 3  ·  CXL basicsThe standard without the jargon

CXL stands for Compute Express Link. It runs over PCIe physical infrastructure and adds coherent memory and device protocols on top. The CXL specification distinguishes three device types. Tanzanite and Marvell's CXL memory-pooling thesis is mostly about Type 3-style memory expansion and pooling.[1]

Type 1
Caching devices or accelerators without local memory. Use CXL.cache to participate in CPU coherency.
Type 2
Accelerators with local memory, such as GPUs, FPGAs, or smart accelerators that expose memory and cache to the host.
Type 3
Memory devices and memory expanders. The category Marvell's Structera-class products mostly target.

CXL's promise is not just faster peripheral I/O. It is making memory part of the data-center fabric.

Section 4  ·  PortfolioMarvell turned the thesis into a portfolio

Marvell's Structera CXL product line targets memory bandwidth and capacity challenges in data centers, with Structera A as a near-memory accelerator family, Structera X as a memory-expansion controller family, and a broader portfolio of accompanying CXL silicon.[2] The product launch material describes Structera A as targeting deep learning recommendation models, ML, and AI workloads with near-memory acceleration, and Structera X as a memory-expansion controller designed for capacity-heavy workloads, with inline compression and a 5nm process node.[3]

Marvell CXL portfolio  ·  how the pieces fit
Structera A
Near-memory accelerator family for DLRM, ML, and AI workloads on CXL-attached memory.
Structera X
CXL memory-expansion controller family, framed around capacity, compression, and DDR support.
Structera S
CXL switch family enabling rack-level memory pooling across CPUs, GPUs, and XPUs.
Alaska P
PCIe / CXL retimers extending signal reach across packages, boards, and racks.
XConn
PCIe / CXL switching IP and platform, acquired in early 2026.
Custom CXL silicon
Cloud-operator-specific CXL silicon built on Marvell's data-center connectivity stack.

Memory pooling moved from demo slide to product portfolio.

Section 5  ·  AI pressureWhy AI makes CXL more important

AI workloads create brutal memory pressure across the system, not only on the accelerator. Marvell's framing around the Structera S launch is explicit: LLM size, expanding context windows, and KV-cache growth are driving memory demand, and CXL-based memory pooling is positioned as a way to improve utilization and application performance without relying only on HBM stacking.[4] The pressure shows up in many places at once.

Larger LLMs with more parameters
Longer context windows per request
Larger KV caches per session
Recommendation models with huge embedding tables
Vector databases and retrieval systems
In-memory analytical databases
Memory-heavy CPU inference
Multi-tenant inference platforms
Analytics and data preprocessing near AI pipelines
Accelerators waiting on data from elsewhere in the system

HBM feeds the GPU. CXL helps feed the system.

Section 6  ·  Structera SThe rack-scale proof point

The Structera S launch is where Marvell turns memory pooling from a single-host expansion story into a rack-level fabric story. Marvell describes the Structera S 30260 as a 260-lane CXL switch supporting CXL 3.0, enabling rack-level memory pooling, with aggregate bandwidth of up to 4 TB/s and the ability to dynamically allocate memory across CPUs, GPUs, XPUs, and other accelerators, with Q3 2026 sampling guidance.[4] Marvell's technical blog adds deployment framing including memory expansion, near-memory acceleration, and pooling examples across CPUs and accelerators.[5]

Structera S lanes
260
260-lane CXL switch per Marvell's Structera S 30260 launch.
Protocol
CXL 3.0
Targets rack-level memory pooling with CXL 3.0 semantics.
Aggregate bandwidth
~ 4 TB/s
Up to 4 TB/s aggregate bandwidth across the switch fabric per Marvell.
Sampling
Q3 2026
Structera S 30260 sampling guidance per Marvell's launch material.

Tanzanite was the memory-pooling idea. Structera S is Marvell's attempt to turn that idea into rack-scale AI infrastructure.

Section 7  ·  XConnThe switching angle

Marvell completed its acquisition of XConn Technologies in February 2026 to expand its PCIe and CXL switching portfolio, framed by the company as strengthening scale-up connectivity for next-generation AI and cloud data-center architectures, with XConn technology expected to support Marvell's UALink scale-up switching roadmap.[6] Reuters reported the deal at approximately US$540 million, with revenue contribution expected as integration progresses.[7] The strategic logic is straightforward. CXL memory pooling depends on a switching and fabric layer. Without switching, CXL is mostly expansion. With switching, it becomes a memory fabric.

XConn deal value
~ US$540M
Reported deal value per Reuters on the Marvell-XConn transaction.
Closing
Feb 2026
Acquisition completion timing per Marvell's investor release.
Scope
PCIe + CXL
PCIe and CXL switching IP and platform technology.
Roadmap fit
UALink
Expected to support Marvell's UALink scale-up switching roadmap.

Marvell is trying to own the open memory-fabric layer around AI infrastructure.

Section 8  ·  CXL 4.0The standard is still moving

The CXL specification has not stopped evolving. CXL 4.0 was announced in late 2025, doubling bandwidth from 64 GT/s to 128 GT/s, adding bundled ports, and enhancing memory RAS (reliability, availability, and serviceability) features, on top of CXL 3.0's dynamic capacity device capability.[8] The same CXL Consortium materials emphasize that pooled memory can have different performance characteristics from local memory and that software must be NUMA-aware or NUMA-optimized to use it well.[8]

CXL 4.0 bandwidth
128 GT/s
Doubled from 64 GT/s, per CXL Consortium materials.
Port model
Bundled
Bundled ports added in CXL 4.0 for higher aggregate throughput.
RAS
Enhanced
Memory reliability, availability, and serviceability features expanded.
From 3.0
DCD
Dynamic capacity device capability from CXL 3.0 carries into 4.0.

CXL is not one product. It is an ecosystem standard trying to become the memory fabric of the data center.

Section 9  ·  LatencyThe trade-off still matters

CXL memory is useful, but it is not identical to local DRAM. Page 10 of the 2022 article framed latency as the largest concern and compared pooled memory latency to CPU-to-CPU NUMA-like latency rather than to local memory.[1] The CXL Consortium itself emphasizes that pooled memory has different performance characteristics and that software needs to be NUMA-optimized to use it effectively.[8] The practical implication is that CXL is best treated as a memory tier with its own characteristics, not as a drop-in replacement for local memory.

Memory tier Strength Weakness Best workload fit
HBM Extreme bandwidth right next to the accelerator Expensive and capacity-limited per stack Accelerator training and high-throughput inference
Local DDR / MRDIMM / SOCAMM Lower-latency CPU memory close to the socket Fixed to server or socket; cannot move with the workload General-purpose CPU workloads and primary host memory
CXL attached memory Capacity expansion beyond DIMM-per-socket limits Higher latency than local DRAM Memory-heavy workloads that tolerate tiering
CXL pooled memory Utilization and sharing across hosts and accelerators Software complexity and latency variability Long-context inference, KV cache, composable cloud, memory bursts
NVMe / SSD Cheap capacity at large scale Much higher latency than any DRAM tier Cold data and storage-heavy pipelines

CXL wins where memory flexibility is worth more than local-memory latency.

Section 10  ·  Not HBMCXL is not replacing HBM

HBM remains the premium memory beside GPUs and AI accelerators. It delivers the bandwidth profile that frontier AI training and high-throughput inference depend on. CXL is not a substitute for HBM bandwidth. CXL's role is more likely capacity expansion, pooling, and utilization around the broader system. The two coexist: HBM for hot accelerator compute, CXL for flexible memory capacity and system-level memory pressure. Framing CXL as an HBM alternative misreads the architecture.

The mistake is asking whether CXL beats HBM. The better question is which memory tier each workload should live in.

Section 11  ·  AI inferenceWhere CXL matters most

CXL may matter more for inference than the discourse often acknowledges. Long-context inference, KV-cache growth, multi-tenant inference platforms, and embedding-heavy systems all create memory allocation problems that map well to tiered and pooled memory rather than to ever-larger per-server DRAM. Marvell's Structera S framing reinforces this: LLM size, context windows, and KV cache are the workload drivers the company highlights for memory pooling.[4]

KV cache expansion for long-context LLMs
Many concurrent users with varying context lengths
Recommendation models with large embedding tables
Vector search and retrieval systems
CPU inference and hybrid CPU/GPU inference
Memory-heavy analytics near AI pipelines
Avoiding overprovisioning memory in every server
Multi-tenant memory bursts across shared pools

Long-context AI does not only create a compute problem. It creates a memory allocation problem.

Section 12  ·  Marvell strategyConnective tissue, not just chips

Marvell's CXL strategy fits inside a broader bet on AI data-center connectivity and custom silicon. CXL sits beside Ethernet, SerDes, retimers, switching, optical interconnect, custom ASICs, and AI infrastructure silicon. The Tanzanite acquisition slotted memory pooling into that strategy, while subsequent moves added switching (XConn) and adjacent scale-up connectivity directions including UALink.[6][7] Marvell's announced Celestial AI acquisition extends the same pattern toward optical I/O at package, system, and rack levels.[9]

Marvell's bet is not just on chips. It is on the connective tissue of AI infrastructure.

Section 13  ·  Proof pointsWhat Marvell must prove

Marvell's open proof points  ·  what AI infrastructure customers will watch
  1. Can CXL pooling deliver useful performance under real AI workloads, not only benchmarks?
  2. Can software stacks become NUMA-aware enough to exploit pooled memory consistently?
  3. Can operators manage latency variability across multi-tenant CXL deployments?
  4. Can CXL switching scale without too much cost, power, and complexity?
  5. Can Structera S integrate smoothly with CPUs, GPUs, XPUs, and memory devices from multiple vendors?
  6. Can CXL pooling improve total cost of ownership enough to justify deployment in production?
  7. Can memory pooling work in multi-tenant cloud environments with strong isolation and security?
  8. Can the ecosystem avoid fragmentation across vendors, generations, and CXL revisions?

The hardware is becoming real. The software and deployment model still have to catch up.

Section 14  ·  EvidenceEvidence ledger

Claim
Evidence
Interpretation
Marvell acquired Tanzanite to fill a CXL gap
The 2022 PDF frames Tanzanite as filling Marvell's memory-pooling IP hole after Cavium, Avera Semi, Inphi, and Innovium.
The acquisition was strategic, not random.
CXL targets composable servers
Page 2 shows CXL Type 1, 2, and 3 devices, and page 5 discusses composable server architecture and TAM framing.
CXL was designed to move memory beyond fixed server boundaries.
Memory pooling has a latency trade-off
Page 10 of the 2022 PDF discusses NUMA-like latency versus local memory.
CXL is a new memory tier, not magic DRAM.
Marvell productized the thesis
Structera A and X target near-memory acceleration and memory expansion, with Structera launch material citing inline compression and 5nm process.
The Tanzanite idea became a real product portfolio.
Structera S is the rack-scale proof point
Marvell launched a 260-lane CXL 3.0 switch with up to 4 TB/s aggregate bandwidth and Q3 2026 sampling guidance.
Marvell is now targeting rack-level memory pooling.
AI makes CXL more relevant
Marvell says LLM size, context windows, and KV cache are driving memory demand.
AI turned memory pooling into an infrastructure issue.
The CXL standard matured
CXL 4.0 doubles bandwidth to 128 GT/s and adds bundled ports and memory RAS features on top of CXL 3.0 Dynamic Capacity Device.
The ecosystem is moving toward larger memory fabrics.
XConn strengthens Marvell's switching strategy
Marvell completed XConn acquisition for PCIe / CXL switching and AI scale-up connectivity, with Reuters reporting approximately US$540M deal value.
Marvell is building the fabric layer, not just endpoints.
CXL will not replace HBM
HBM remains the high-bandwidth accelerator memory tier; the 2022 PDF frames CXL as composable infrastructure rather than HBM substitute.
CXL is more likely to become the flexible capacity / utilization tier.

Section 15  ·  Risk registerRisks and limitations

This essay is an analysis of public disclosures and historical context. It is not investment advice. The honest risks against the read above run in several directions, and they are listed here so the argument can be stress-tested.

CXL pooled memory is not equivalent to local DRAM. Latency variability and software-stack maturity remain the biggest practical risks.
Marvell performance claims (260 lanes, 4 TB/s aggregate, near-memory acceleration) are Marvell claims and should be tracked against independent benchmarks once shipping.
Not all AI workloads benefit equally from CXL memory pooling. Workloads with extreme bandwidth needs still belong on HBM, and CXL is best treated as a tier, not a replacement.
CXL ecosystem adoption depends on consistent vendor support across CPUs, GPUs, switches, and memory devices. Fragmentation can slow deployment.
Hyperscaler in-house CXL silicon could compress the addressable market for merchant CXL providers over time.
Competing scale-up connectivity efforts (UALink, NVLink, OCP MGX) could change the architectural balance for memory pooling and pooling-adjacent fabrics.
CXL switching adds cost, power, and complexity. Some operators may prefer simpler memory-expansion deployments over true pooling for several years.
Multi-tenant security and isolation requirements may slow real-world deployments of pooled memory in shared environments.
CXL specification revisions move quickly. Customers will need to manage compatibility across CXL 3.0, 4.0, and beyond.
An AI demand normalization could slow CXL adoption timelines that depend on continued capex acceleration.

Section 16  ·  Bottom lineBottom line

Bottom line

The 2022 Tanzanite article was right that CXL memory pooling would matter for composable servers. In 2026, the thesis is stronger because AI has made memory capacity, bandwidth, utilization, and KV-cache economics central infrastructure problems. Marvell has turned the idea into a serious portfolio with Structera A, Structera X, Structera S, Alaska P, XConn switching, and custom CXL silicon.

But the realistic role of CXL is not to replace HBM. HBM remains the high-bandwidth memory tier for accelerators. CXL becomes the flexible memory tier around the system: useful for expansion, pooling, utilization, long-context inference, KV cache, memory-heavy analytics, and composable AI infrastructure.

The AI memory wall is not only about faster memory. It is about putting the right memory in the right place at the right time.

Section 17  ·  DefinitionsGlossary

CXL
Compute Express Link. An open standard for cache-coherent and memory-coherent interconnect over PCIe physical infrastructure.
PCIe
Peripheral Component Interconnect Express. The dominant high-speed interconnect for CPU-to-device communication in modern servers.
CXL Type 1
Caching devices and accelerators that use CXL.cache to participate in CPU coherency without local memory exposure.
CXL Type 2
Accelerators with local memory (GPUs, FPGAs, smart accelerators) that expose memory and cache to the host.
CXL Type 3
Memory devices and memory expanders. The category Structera-class products mostly target.
Memory expansion
Adding more memory to a single host using CXL beyond what DIMM slots alone allow.
Memory pooling
Sharing CXL memory across multiple hosts or accelerators, often via switching, with dynamic allocation.
Memory fabric
An interconnect layer that treats memory as a shared, addressable resource across a rack or larger system, rather than as private DRAM behind each socket.
Composable server
A server architecture in which compute, memory, storage, and accelerators are allocated dynamically to match workload needs rather than fixed at build time.
DRAM utilization
The fraction of installed DRAM that is actually used by running workloads. Low utilization is expensive because DRAM is a large server cost line.
NUMA
Non-Uniform Memory Access. An architecture in which memory has different latencies depending on which CPU socket or domain accesses it. CXL pooled memory looks NUMA-like to software.
Local DRAM
DIMM-attached memory directly tied to a CPU socket, with the lowest latency available outside the CPU cache.
Remote memory
Memory accessed across an interconnect rather than directly attached to the local socket. CXL pooled memory is a form of remote memory.
HBM
High Bandwidth Memory. Stacked DRAM packaged with accelerators for very high bandwidth and limited capacity per stack.
KV cache
Key-value cache used by transformer LLMs to remember past tokens during inference. Grows with context length and concurrency.
Structera A
Marvell's near-memory accelerator family in the Structera CXL product line, framed at DLRM, ML, and AI workloads.
Structera X
Marvell's CXL memory-expansion controller family, framed around capacity, compression, and DDR support.
Structera S
Marvell's CXL switch family, including the Structera S 30260 with up to 4 TB/s aggregate bandwidth for rack-level memory pooling.
Retimer
A signal-conditioning device that extends PCIe / CXL reach across packages, boards, and racks. Marvell's Alaska P is an example.
XConn
PCIe and CXL switching technology acquired by Marvell in early 2026 to expand its scale-up connectivity portfolio.
UALink
An open scale-up interconnect specification for tightly coupled AI accelerators across servers and racks. Targeted by multiple vendors as an alternative scale-up fabric.
Near-memory acceleration
Compute placed close to memory (in the CXL memory device itself, for example) to reduce data movement for memory-heavy workloads such as DLRM.

Section 18  ·  MethodSources and method notes

How this essay reads sources

The 2022 SemiAnalysis Tanzanite piece is treated as historical context for the CXL Type 1 / 2 / 3 framing, the composable server thesis, the DRAM utilization problem, the rack-scale CXL memory-pooling concept, and the latency trade-off discussion. Marvell product claims (Structera lane counts, aggregate bandwidth, process node, near-memory acceleration framing) are treated as Marvell's claims rather than as independently verified numbers. The CXL Consortium materials are used at the specification level, and the company is explicit that pooled memory may have different performance characteristics and that software needs to be NUMA-optimized.

The 2026 read is built primarily from Marvell's Structera CXL product page, the Structera launch release, the Structera S launch release, the Structera S technical blog, the CXL Consortium 4.0 Q&A, Marvell's XConn acquisition release, Reuters on the XConn deal, and (as broader connectivity context) the Marvell-Celestial AI acquisition release. The structural arguments that CXL becomes the flexible memory tier around AI infrastructure, that latency keeps CXL from being a transparent HBM replacement, and that software maturity is the binding constraint are independent analysis.

Footnotes  ·  primary sources

  1. SemiAnalysis, “Marvell Acquires Tanzanite Silicon To Enable Composable Server Architectures Using CXL Based Memory Expansion And Pooling,” 2022 (PDF supplied by author). Historical anchor used in this essay for the CXL Type 1 / 2 / 3 framing on page 2, the Micron-cited CXL TAM chart on page 5, the rack-scale CXL Type 3 memory-pooling concept on page 6, the Tanzanite memory-pooling demo across multiple host CPUs over PCIe / CXL on page 8, the latency penalty and NUMA-like comparison on page 10, and the single-host expansion versus true memory pooling contrast on page 11.
  2. Marvell, “Structera CXL Product Line,” marvell.com/…/cxl. Source for Marvell's official Structera CXL product framing, the Structera A near-memory accelerator family, the Structera X memory-expansion controller family, the DDR4 and DDR5 support context, inline compression, encryption, and secure-boot capabilities, and the broader CXL portfolio framing used in this essay.
  3. Marvell, “Marvell Introduces Breakthrough Structera CXL Product Line to Address Server Memory Bandwidth and Capacity Challenges in Cloud Data Centers,” marvell.com/…/structera-launch. Source for the official 2024 Structera launch, Structera A for DLRM, ML, and AI workloads, Structera X memory-expansion framing, four memory channels, inline compression, the 5nm process context, and the custom CXL silicon for cloud-operator framing.
  4. Marvell, “Marvell Next-Gen CXL Switch Memory Pooling Breaks the AI Memory Wall,” marvell.com/…/structera-s-launch. Source for the Structera S 30260 framing as a 260-lane CXL switch with CXL 3.0 support, rack-level memory pooling, up to 4 TB/s aggregate bandwidth, dynamic memory allocation across CPUs, GPUs, XPUs, and other accelerators, the LLM size / context window / KV-cache memory-wall framing, and the Q3 2026 sampling guidance.
  5. Marvell, “Structera S: Scaling the AI Memory Wall with CXL Switching,” marvell.com/…/structera-s-blog. Source for the Structera S deployment examples, the memory-expansion vs near-memory acceleration vs pooling framing, the 4 TB/s cumulative bandwidth context, and the CXL switching explanation used in this essay.
  6. Marvell, “Marvell Completes Acquisition of XConn Technologies,” investor.marvell.com/…/marvell-completes-xconn. Source for Marvell completing the XConn acquisition in February 2026, the PCIe / CXL switching portfolio expansion, the AI and cloud data-center scale-up connectivity framing, the support for Marvell's UALink scale-up switching roadmap, and the multi-rack deployment context.
  7. Reuters, “Marvell to buy networking equipment firm XConn in $540 million deal amid AI demand,” reuters.com/…/marvell-xconn-540m. Source for the approximately US$540M deal value, the revenue contribution expectations, and the AI data-center infrastructure context cited in this essay.
  8. CXL Consortium, “Introducing the CXL 4.0 Specification — Webinar Q&A Recap,” computeexpresslink.org/…/cxl-4-0-qa. Source for CXL 4.0's 128 GT/s bandwidth doubling, the bundled ports addition, the memory RAS enhancements, the carryover of CXL 3.0's Dynamic Capacity Device capability, the NUMA-optimized software caveat, and the framing that pooled memory has different performance characteristics from local memory.
  9. Marvell, “Marvell to Acquire Celestial AI, Accelerating Scale-Up Connectivity for Next-Generation Data Centers,” investor.marvell.com/…/marvell-celestial-ai. Used here only as broader Marvell connectivity context, including the package, system, and rack-level optical I/O framing and the AI scale-up connectivity strategy. Not used as a CXL-specific source.
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