Essay No. 068  ·  Semiconductors / Geopolitics / AI Infrastructure
Semiconductors AI Infrastructure Geopolitics Supply Chain TSMC ASML CHIPS Act Advanced Packaging Industrial Policy

I, Semiconductor: Regionalization Became the New Cost of AI Sovereignty CHIPS Act TSMC Arizona ASML EU Chips Act Rapidus Advanced Packaging OSAT AI Sovereignty Trusted Redundancy

The chip supply chain is not becoming independent. It is becoming redundantly globalized, and that resilience comes with a much higher price tag.

PM
PUGALENTHI MAGENDRAN
May 27, 2026  ·  Research memo  ·  Updating a 2022 supply-chain thesis
16 MIN
Thesis
The world is not fully deglobalizing semiconductors. That is impossible. What is happening is more specific: governments and companies are duplicating critical parts of the semiconductor supply chain across trusted regions because AI, national security, Taiwan risk, export controls, and chip shortages made the old efficiency-first model too fragile. The result is not self-sufficiency. It is trusted redundancy. That makes the system safer, but also more expensive, less efficient, and more capital-intensive.
In this essay
  1. Historical context: what the 2022 article got right
  2. The 2026 update: regionalization is now policy
  3. The US buildout is real, but not independence
  4. TSMC is regionalizing, but Taiwan remains the engine room
  5. Europe shows the gap between ambition and execution
  6. Japan matters because the upstream stack matters
  7. ASML proves why full self-sufficiency is fantasy
  8. Equipment spending is the clearest proof
  9. The cost of resilience
  10. AI sovereignty makes regionalization permanent
  11. The new semiconductor map
  12. Evidence ledger
  13. Risks and limitations
  14. Bottom line
  15. Glossary
  16. Sources and method notes
Executive summary
  • The 2022 thesis warned that semiconductor supply chains were globally connected but dangerously concentrated.
  • By 2026, regionalization is no longer a prediction. It is official industrial policy across the US, Europe, Japan, Taiwan, Korea, India, and China.
  • The new model is not national self-sufficiency. It is trusted redundancy across allied or strategically important regions.
  • Regionalization makes the system more resilient, but also more expensive because smaller duplicated fabs are less efficient than giant concentrated fabs.
  • AI demand makes this permanent by increasing demand for leading-edge logic, HBM, advanced packaging, power, networking, storage, and fab equipment.

Section 1  ·  Historical frameWhat the 2022 article got right

The 2022 SemiAnalysis piece, I, Semiconductor: The Regionalization Of Semiconductors Due To Global Supply Chain Instability, opened with the I, Pencil analogy.[1] Even a pencil, the simplest possible product, requires inputs from a dozen countries. Semiconductors are vastly more complex. The piece used that contrast to argue that the chip supply chain was fragile because it had been optimized for efficiency, not resilience, with every step placed where scale, cost, specialization, and supplier density were strongest.

The concentration map mattered. Silicon wafers were highly concentrated in Japan, Taiwan, Singapore, and South Korea. Lithography dependency was not only ASML in the Netherlands. Japan was critical through Tokyo Electron coaters and developers and photoresist suppliers like Shin-Etsu, JSR, and Tokyo Ohka Kogyo.[1] Advanced logic manufacturing was concentrated in Taiwan and South Korea. DRAM and NAND production were concentrated in East Asia. OSAT, packaging, and test were heavily concentrated in Asia, and even chips fabricated in the West often traveled to Asia for assembly. The page 2 pencil diagram, the page 3 silicon boule and wafer creation visual, the page 6 Japanese lithography dependency callout, and the page 7 and page 10 concentration charts all carried the same argument.[1]

The 2022 piece also made a structural prediction. Regionalization would raise capital intensity because smaller duplicated fabs are less efficient than large concentrated giga-fabs. Page 14 connected regionalization directly to higher capex and argued that wafer fabrication equipment suppliers would benefit from this structural shift.[1] Four years later, that argument is not a forecast anymore. It is the published industry plan.

Section 2  ·  Now policy, not theoryThe 2026 update: regionalization is industrial policy

The 2022 argument has become reality. The US CHIPS and Science Act, the European Chips Act, Japan's Rapidus push, TSMC's Arizona and Kumamoto expansions, ESMC in Dresden, India's packaging incentives, Korea's memory and foundry support, and China's self-sufficiency drive all reflect the same shift. The OECD's 2025 semiconductor value-chain mapping report describes the chain as complex, distributed, deeply interconnected, and exposed to concentration and bottleneck risks across multiple critical inputs, which is the policy-level validation of the same picture.[2]

The distinction that matters is between two words that sound similar but mean different things. Deglobalization implies countries trying to rebuild the entire chip stack inside their borders. That is not realistic because the stack is too complex and too interdependent. Regionalization means duplicating selected critical capacity in trusted regions while still relying on the global ecosystem for the rest. The result is not independence. The result is reduced exposure to single-region failure.

The semiconductor supply chain is not deglobalizing. It is becoming redundantly globalized.

Old model  ·  pre-2022
Efficiency first
Place every step where scale, cost, specialization, and supplier density were strongest. Optimize for throughput and unit cost across one tightly connected global chain.
New model  ·  2026
Resilience first
Duplicate critical capacity across trusted regions even when it is more expensive. Accept lower efficiency in exchange for reduced exposure to single-region failure.

Section 3  ·  United StatesThe US buildout is real, but not independence

The US CHIPS and Science Act funding is structured to backstop the US semiconductor ecosystem at scale. NIST describes CHIPS for America as a roughly US$50 billion commitment, with about US$39 billion for manufacturing incentives and about US$11 billion for research and development.[3] That is the public spend. The private response is larger. The Semiconductor Industry Association tracks more than 140 semiconductor ecosystem projects across more than 30 states, more than US$645 billion in private investment since 2020, and more than 525,000 US jobs supported across those projects.[4]

CHIPS Act total
~ US$50B
Federal commitment under the CHIPS and Science Act, per NIST CHIPS for America.
Manufacturing incentives
~ US$39B
Funding directed at fab construction, expansion, and capacity in the US.
R&D commitment
~ US$11B
Funding for semiconductor R&D programs and the National Semiconductor Technology Center.
Private investment since 2020
~ US$645B+
Tracked private commitments across 140+ projects in 30+ states, per SIA.

The honest interpretation is narrower than the headlines. The CHIPS Act does not make the US semiconductor-independent. It makes the US less exposed to single-region failure. America can build more fabs, but it still needs ASML lithography from the Netherlands, Japanese materials and photoresist, Taiwanese foundry knowledge, Korean memory, global packaging and test, and imported talent. The new model is allied redundancy, not self-sufficiency.

America can build more fabs, but it still needs ASML lithography, Japanese materials, Taiwanese foundry knowledge, Korean memory, global packaging, and imported talent.

Section 4  ·  TSMCRegionalizing, but Taiwan remains the engine room

TSMC's 2025 Annual Report frames Arizona as a multi-phase regional buildout. The first Arizona facility began volume production of 4nm-class technology in Q4 2024. A second Arizona facility is being prepared for 3nm and more advanced technologies. Construction of a third Arizona facility began in 2025. TSMC continues to invest in Taiwan for N2, advanced nodes, and advanced packaging, and is expanding through ESMC in Dresden and JASM in Kumamoto.[5]

The right reading is geographic flexibility, not relocation. TSMC is not moving out of Taiwan. The deepest technical center, the densest engineering talent pool, the most ambitious node ramps, and the most advanced packaging capacity all remain anchored on the island. Arizona, Kumamoto, and Dresden are extensions, designed to give TSMC and its customers a regional answer to a Taiwan-only failure mode rather than a Taiwan replacement.

TSMC is regionalizing customer-facing capacity. It is not moving the heart of its technology engine out of Taiwan.

Section 5  ·  EuropeThe gap between ambition and execution

The European Chips Act entered into force on 21 September 2023, with the explicit objectives of strengthening the semiconductor ecosystem, improving supply-chain resilience, reducing strategic dependencies, and doubling Europe's global semiconductor market share to 20% by 2030.[6] The European Commission's tracking page lists more than €31.5 billion of approved public and private investment in first-of-a-kind facilities under the act.[6]

The European Court of Auditors looked at the same target with less optimism. Its 2025 report concluded that the EU's 20% market share target by 2030 is very unlikely to be achieved, and that the realistic forecast is closer to 11.7% by 2030 on current trajectories.[7] Europe has real projects. The ambition is larger than the execution capacity. That is not unique to Europe. It is the same gap, in slightly different forms, that every region is running into once the policy language collides with workforce, supplier ecosystem, and capital reality.

Everyone wants semiconductor sovereignty. Very few regions can afford the full stack.

Section 6  ·  JapanWhy the upstream stack matters

The 2022 source highlighted Japan's structural role in photoresist, coaters and developers, wafers, and specialty materials.[1] Four years later, that role has been reinforced. Japan is doubling down upstream in materials and tools, and is also trying to re-enter advanced logic through Rapidus. In April 2026, Japan approved an additional 631.5 billion yen, roughly US$3.96 billion, in funding for Rapidus, with total R&D assistance reaching approximately 2.354 trillion yen, and Rapidus targeting 2nm-class logic with mass production planned for fiscal 2027.[8]

Whether Rapidus reaches a mature 2nm ramp on its declared timeline is a separate question. The structural point stands regardless. Japan does not need to replace TSMC to matter. It already matters because the rest of the world needs Japanese materials, wafers, chemicals, equipment, and precision manufacturing to operate at all. Strengthening the upstream stack is the more important Japanese contribution to global resilience, even when the headline attention follows the logic projects.

Section 7  ·  ASMLWhy full self-sufficiency is fantasy

ASML's 2025 numbers show the scale of a single chokepoint. The 2025 Annual Report and the Q4 2025 results release describe net sales of approximately €32.7 billion, gross margin of 52.8%, R&D of approximately €4.7 billion, net income of approximately €9.6 billion, and a backlog of approximately €38.8 billion.[9][10] ASML remains the key chokepoint for EUV lithography, including the High-NA generation. No country can buy its way around that chokepoint in a few years.

ASML 2025 net sales
~ €32.7B
Per ASML 2025 Annual Report.
Gross margin
52.8%
High structural margin reflects the chokepoint position.
R&D
~ €4.7B
Continued lithography roadmap investment, including High-NA.
Backlog
~ €38.8B
Per Q4 2025 results, showing multi-year demand visibility.

A country can subsidize fabs. It cannot quickly recreate ASML, Zeiss optics, Cymer light sources, the broader supplier network, and decades of lithography learning. Even if a parallel ecosystem were funded today, the realistic timeline runs into the same physics, the same precision-manufacturing constraints, and the same talent shortage that ASML itself faces.

Regionalization can duplicate fabs faster than it can duplicate the toolchain.

Section 8  ·  Equipment cycleThe clearest proof is the capex

SEMI's 300mm fab equipment forecast turns the regionalization argument into a number. SEMI projects global 300mm fab equipment spending of approximately US$374 billion from 2026 to 2028, with US$116 billion in 2026, US$120 billion in 2027, and US$138 billion in 2028. Logic and micro investment is projected at approximately US$175 billion over the three-year window. Memory investment is projected at approximately US$136 billion, supported by AI training, inference, HBM, and storage demand. SEMI explicitly links the spending cycle to fab regionalization, AI chip demand, self-sufficiency efforts, localized industrial ecosystems, and supply-chain restructuring.[11]

SEMI 300mm fab equipment forecast  ·  2026 to 2028
2026
US$116B
300mm fab equipment
2027
US$120B
300mm fab equipment
2028
US$138B
300mm fab equipment
Three-year total
~ US$374B

That capex cycle is the 2022 capital-intensity argument made tangible. Regionalization raises structural capex because the same total wafer demand is now being served by more, smaller, and less utilized fabs spread across more regions. AI raises absolute demand on top of that. The two effects compound. Equipment suppliers, materials suppliers, and packaging tool vendors all sit on top of that compounded curve.

Regionalization raises structural capex. AI raises demand. Together, they create a massive equipment cycle.

Section 9  ·  Trade-offThe cost of resilience

Regionalization is not free. It is expensive insurance. The honest version of the story has both sides on the page at the same time. The benefits are real. The costs are also real.

Benefits of regionalization
  • Reduces single-region failure risk across Taiwan, Korea, Japan, and adjacent geographies.
  • Gives governments more control over critical infrastructure.
  • Improves supply assurance for defense, AI, automotive, energy, and cloud customers.
  • Creates local jobs, training pipelines, and industrial capability.
  • Gives companies geopolitical optionality across allied blocs.
  • Strengthens trusted-bloc cooperation on export controls, IP, and security.
Costs of regionalization
  • Smaller duplicated fabs are less efficient than large concentrated giga-fabs.
  • Tool utilization may be lower at duplicated capacity.
  • Labor and talent shortages get worse, not better, at the new locations.
  • Supplier ecosystems take years, sometimes decades, to build.
  • Subsidies can reward less efficient capacity by design.
  • Packaging, materials, and specialty steps may remain concentrated even after fabs are built.
  • Capital intensity rises across the industry.

Regionalization is not free resilience. It is expensive insurance.

Section 10  ·  AI sovereigntyWhat makes regionalization permanent

AI changes the economics because governments now treat compute as strategic infrastructure on the same level as power, telecoms, and energy. AI demand pulls hard on leading-edge logic, on HBM and advanced memory, on advanced packaging like CoWoS-style integration, on power and networking inside the data center, and on storage at the system level. Every one of those layers has a geographic concentration story attached to it. Every one of those layers is now a target of regionalization policy somewhere in the world.

That is what flips regionalization from a chip-cycle response into a structural shift. A normal chip cycle ends. Industrial policy aimed at AI sovereignty does not. Once compute becomes a sovereign concern, the political logic for duplicated capacity outlives any single shortage. That is why the equipment forecast extends through 2028 and why the project tracker keeps adding lines. AI demand is the engine that makes regionalization permanent.

The chip shortage made regionalization urgent. AI made it permanent.

Section 11  ·  The new mapLayer by layer, where the chokepoints live

Layer Old concentration Regionalization response Hard-to-duplicate chokepoint
Wafers Japan, Taiwan, South Korea, Singapore More allied materials and wafer capacity Purity, crystal growth, specialty wafers
Photoresist and chemicals Japan-heavy (Shin-Etsu, JSR, TOK, Sumitomo) Supply diversification, dual sourcing, EU and US programs Advanced EUV resist know-how and process integration
Lithography Netherlands (ASML) plus Japanese support tools Allied export controls and tool allocation policy ASML EUV and High-NA platform
Fabs Taiwan, Korea, East Asia US, EU, Japan, India, Korea incentive programs Yield learning, scale, engineering talent
Memory Korea, Taiwan, Japan, Singapore, China US and allied memory fabs and HBM capacity expansion HBM stacking, DRAM scaling, NAND scale
Packaging and test China, Taiwan, Malaysia, Singapore, Vietnam US, India, EU packaging push OSAT scale, substrates, skilled labor pools
EDA and IP US-heavy Export controls, domestic-alternative programs Software ecosystems, IP libraries, design tools

The pattern across the rows is consistent. Every layer is being touched by some regionalization policy. Every layer still has a chokepoint that cannot be duplicated on a policy timeline. The map gets safer at the layer that can be duplicated. The map stays fragile at the layer that cannot. That is the honest 2026 description of the chip supply chain.

Section 12  ·  EvidenceEvidence ledger

Claim
Evidence
Interpretation
2022 concentration thesis was right
Original article mapped wafer, lithography, fab, memory, OSAT, and packaging chokepoints across Japan, Taiwan, Korea, China, and Southeast Asia.
The supply chain was global but not balanced.
US buildout is real
SIA tracks more than 140 projects, 30+ states, more than US$645B in private investment since 2020, and more than 525,000 jobs supported.
Regionalization has become capital deployment, not slogan.
CHIPS Act is risk reduction
NIST CHIPS for America: approximately US$50B total, US$39B manufacturing incentives, US$11B R&D.
The US is building resilience, not full independence.
TSMC is regionalizing capacity
Arizona Fab 1 in 4nm volume production, Fab 2 for 3nm and beyond, Fab 3 construction in 2025, Japan and Europe expansions, continued Taiwan investment.
Geographic flexibility around Taiwan, not Taiwan replacement.
Europe has ambition but execution risk
EU Chips Act 20% market share target by 2030; ECA forecast points to approximately 11.7% by 2030.
Sovereignty is harder than policy language.
Japan is rebuilding advanced logic
Additional 631.5B yen approved for Rapidus in April 2026; cumulative R&D assistance approximately 2.354T yen; 2nm-class target with mass production in fiscal 2027.
State capital is being used to re-enter leading-edge logic.
ASML remains a chokepoint
2025 net sales of approximately €32.7B, 52.8% gross margin, R&D of approximately €4.7B, backlog of approximately €38.8B, dominant EUV and High-NA role.
The toolchain is harder to duplicate than fabs.
Equipment suppliers benefit
SEMI forecasts approximately US$374B 300mm fab equipment spending from 2026 to 2028, with logic/micro at approximately US$175B and memory at approximately US$136B.
Regionalization plus AI demand drives a large equipment cycle.
AI makes regionalization permanent
AI demand on leading-edge logic, HBM, advanced packaging, power, networking, and storage; governments treating compute as strategic infrastructure.
Compute is now sovereign-grade infrastructure.

Section 13  ·  Risk registerRisks and limitations

This essay is an analysis of public disclosures and historical context. It is not investment advice. The honest risks against the read above run in several directions, not only against regionalization optimists.

Subsidy cycles can reverse. Political changes in any of the major regions could compress incentive flows before duplicated capacity reaches mature utilization.
Talent shortages at new fab geographies can delay ramps and erode the cost case for duplicated capacity, even when capital is committed.
A serious Taiwan disruption would expose how thin redundancy actually is at leading-edge nodes, regardless of how many projects are tracked elsewhere.
Export control escalation could fragment tool, materials, and IP flows beyond what current regional plans assume, raising costs further.
An AI demand normalization, or a hyperscaler pullback, could leave a large duplicated capacity footprint under-utilized and economically painful for years.
ASML and Japanese chokepoint suppliers could face capacity or yield issues that ripple across every regional buildout simultaneously.
European execution may continue to lag policy ambition, leaving Europe more dependent on US and Asian capacity than the EU Chips Act language implies.
Rapidus may slip on its 2nm timeline. A slip would not break Japan's upstream role but would reset expectations for Japanese leading-edge logic.
China's own self-sufficiency push could reshape demand and competitive dynamics inside trusted-bloc regionalization, especially at trailing and mature nodes.
Capital cost inflation in fabs, tools, materials, and packaging may exceed the planning assumptions baked into current incentive programs.

Section 14  ·  Bottom lineBottom line

Bottom line

The 2022 prediction was right, but the 2026 version needs to be more precise. Semiconductors are not deglobalizing. They are becoming regionally duplicated around trusted blocs. That makes the system safer, but also more expensive. The cost of AI sovereignty is higher capex, duplicated fabs, lower efficiency, workforce strain, and dependence on chokepoint suppliers like ASML, Japanese materials companies, US EDA, and Asian packaging ecosystems.

The world is not rebuilding one semiconductor supply chain. It is building several overlapping safety nets around the same fragile machine.

Section 15  ·  DefinitionsGlossary

Semiconductor regionalization
The deliberate duplication of selected critical semiconductor capacity across multiple trusted regions to reduce single-region failure risk, even at the cost of efficiency.
Trusted redundancy
Building redundant capacity inside allied or strategically aligned regions, rather than attempting full domestic self-sufficiency.
Fab
A semiconductor fabrication facility. Where wafers are processed into chips through hundreds of steps including lithography, deposition, etch, implant, and metrology.
Giga-fab
An informal term for very large, highly concentrated fabs that process tens of thousands of wafers per month and capture significant efficiency through scale.
Wafer
A thin slice of highly pure silicon, usually 300 mm in diameter, on which semiconductor devices are built.
Photoresist
A light-sensitive material spun onto a wafer so that patterns can be transferred from a mask to the wafer during lithography. EUV resist is a specialty subset.
EUV
Extreme ultraviolet lithography. The 13.5 nm-wavelength patterning technology used at leading-edge logic and DRAM nodes, supplied by ASML.
EDA
Electronic design automation. The software ecosystem used to design, verify, and validate semiconductor chips. Dominated by US-headquartered vendors.
OSAT
Outsourced Semiconductor Assembly and Test. Companies that handle packaging, assembly, and test services after wafer fabrication.
Advanced packaging
A family of techniques (2.5D, 3D, CoWoS, InFO, SoIC, hybrid bonding) that integrate multiple dies in a single package, central to AI accelerator scaling.
HBM
High Bandwidth Memory. Stacked DRAM integrated with logic dies through advanced packaging. A key AI accelerator bandwidth bottleneck.
CoWoS
Chip-on-Wafer-on-Substrate. TSMC's 2.5D advanced packaging platform that integrates logic dies and HBM stacks on a silicon interposer.
Capital intensity
The amount of capital required to produce a unit of output. Higher capital intensity means more spend per wafer or per chip, often driven by smaller, duplicated fabs.
Yield learning
The process of improving the fraction of good chips per wafer over time. Yield learning is one of the hardest things to duplicate in a new region.
Tool utilization
The proportion of installed semiconductor tool capacity that is actively producing wafers. Lower utilization spreads fixed costs across fewer wafers.
Supply-chain chokepoint
A point in the value chain where a small number of suppliers control most of the capacity, making the chain sensitive to any disruption at that point.

Section 16  ·  MethodSources and method notes

How this essay reads sources

The 2022 SemiAnalysis piece is treated as historical context, particularly for the I, Pencil analogy, the geographic concentration map, the Japanese lithography dependency, and the capital intensity argument. The 2026 read is built from policy and corporate primary sources: the OECD value-chain mapping, NIST CHIPS for America, the SIA investment tracker, TSMC's annual reporting, the European Commission Chips Act page, the European Court of Auditors 2025 report, Reuters on Rapidus funding, ASML's annual report and Q4 2025 results, and the SEMI 300mm fab equipment forecast.

Company and government claims about future market share, funding totals, capacity ramps, and capex outlooks are treated as company and government claims, not as forecasts that this memo endorses. The structural argument that regionalization is now policy, that AI makes it permanent, and that chokepoint suppliers remain critical is independent analysis. The numbers behind it are not.

Footnotes  ·  primary sources

  1. SemiAnalysis, “I, Semiconductor: The Regionalization Of Semiconductors Due To Global Supply Chain Instability,” 2022 (PDF supplied by author). Historical anchor used in this essay for the I, Pencil analogy on page 2, the silicon boule and wafer creation on page 3, the Japanese lithography dependency on page 6, the geographic concentration on pages 7 and 10, the capital intensity argument on page 14, and the framing of wafers, photoresist, lithography, fabs, memory, OSAT, and packaging concentration.
  2. OECD, “Mapping the Semiconductor Value Chain,” 2025 oecd.org/…/mapping-the-semiconductor-value-chain. Source for the modern policy-level mapping of the value chain as complex, distributed, deeply interconnected, and exposed to concentration and bottleneck risks across multiple critical inputs.
  3. NIST, “CHIPS for America,” nist.gov/chips. Source for the structure of the CHIPS and Science Act, with approximately US$50B total, US$39B for manufacturing incentives, and US$11B for R&D and related programs.
  4. Semiconductor Industry Association, “Chip Supply Chain Investments,” semiconductors.org/chip-supply-chain-investments. Source for the tracker of more than 140 semiconductor ecosystem projects across more than 30 states, more than US$645B in private investment since 2020, and more than 525,000 US jobs supported.
  5. TSMC, “2025 Annual Report,” investor.tsmc.com/…/2025. Source for Arizona Fab 1 entering volume production of 4nm-class technology in Q4 2024, Arizona Fab 2 being prepared for 3nm and more advanced nodes, Arizona Fab 3 construction starting in 2025, continued Taiwan investment in N2 and advanced packaging, and Japan and Europe expansion.
  6. European Commission, “European Chips Act,” digital-strategy.ec.europa.eu/…/european-chips-act. Source for the European Chips Act entering into force on 21 September 2023, the goal of doubling Europe's global semiconductor market share to 20%, the resilience and dependency reduction objectives, and the more than €31.5B of approved public and private investment in first-of-a-kind facilities.
  7. European Court of Auditors, “Special Report on the EU Chips Act,” 2025 eca.europa.eu/…/sr-2025-12. Source for the assessment that the EU's 20% global market share target by 2030 is very unlikely to be achieved, with a realistic forecast closer to 11.7% by 2030.
  8. Reuters, “Japan approves additional ~US$4B for chipmaker Rapidus,” April 2026 reuters.com/…/japan-approves-rapidus-2026-04-11. Source for Japan approving an additional 631.5B yen for Rapidus, the cumulative R&D assistance reaching approximately 2.354T yen, the 2nm-class logic target, and the fiscal 2027 mass production plan.
  9. ASML, “2025 Annual Report,” asml.com/investors/annual-report. Source for €32.7B 2025 net sales, 52.8% gross margin, €4.7B R&D, and EUV and lithography chokepoint context.
  10. ASML, “Q4 2025 Financial Results,” asml.com/…/q4-2025-financial-results. Source for approximately €9.6B net income, €38.8B backlog, High-NA revenue recognition context, and 2026 outlook framing.
  11. SEMI, “Global 300mm Fab Equipment Spending Expected to Total US$374B Over Next Three Years,” semi.org/…/300mm-fab-equipment-374-billion. Source for approximately US$374B global 300mm fab equipment spending from 2026 to 2028 (US$116B in 2026, US$120B in 2027, US$138B in 2028), logic and micro equipment investment of approximately US$175B, memory equipment investment of approximately US$136B, and the explicit linkage to fab regionalization, AI chip demand, self-sufficiency efforts, localized industrial ecosystems, and supply-chain restructuring.
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