Essay No. 064 · TSMC Capex & AI Industrial Plan
TSMC's Capex Became the AI Industrial Plan. Original analysis Not investment advice
In 2022, TSMC's $40B to $44B capex plan looked like a foundry gauntlet against Intel and Samsung. In 2026, the story is bigger: TSMC's spending is becoming the physical buildout of the AI compute economy.
TSMC's capex is no longer just foundry spending. It is the industrial plan behind AI compute — concentrated on 2 nm, 3 nm, CoWoS, SoIC, advanced packaging and HPC capacity, the exact bottlenecks AI demand has created.
In 2022, TSMC shocked the semiconductor world with a $40B to $44B capital expenditure plan.
Intel and Samsung were promising aggressive roadmaps. TSMC responded with capital. But the deeper point was not that TSMC simply spent more. It was that TSMC spent into the right bottlenecks: advanced nodes, packaging, yield learning, and customer-backed capacity. By 2026, that spending has become the physical buildout of AI compute.
TSMC's capex is not just spending. It is a map of where the AI economy expects scarcity.
Section 01 What the 2022 TSMC capex article got right
The 2022 SemiAnalysis piece on TSMC's capex gauntlet is the historical anchor for this essay[1]. It framed TSMC's $40B to $44B 2022 capex plan as a gauntlet against Intel and Samsung, noting that 2021 planned capex of $25B to $28B had landed around $30B and that 2022 expectations had been raised from $30B to $35B up to $40B to $44B. The piece argued that Intel and Samsung would struggle to keep up at that scale and cited customer commitments anchoring the spend: TSMC had collected $6.7B of customer prepayments over six months, alongside Nvidia advance payments inside broader long-term supply agreements.
The mix mattered as much as the headline. The piece said 70% to 80% of 2022 capex was allocated to 7 nm, 5 nm, 3 nm, and 2 nm, with around 10% directed at masks and advanced packaging including CoWoS, SoIC, and InFO. A 12-inch-equivalent wafer ASP chart on page 5 showed average pricing rising as mix shifted toward leading edge and specialty technologies. The 2021 platform-revenue chart on page 7 had smartphones at 44% and HPC at 37%, with HPC already called the largest absolute-dollar growth sector[1].
- 2022 capex plan raised to $40B-$44B, up from $30B-$35B prior expectation.
- 2021 planned $25B-$28B; actual ~$30B.
- 70%-80% of 2022 capex directed to 7 nm, 5 nm, 3 nm, 2 nm.
- ~10% directed to masks and advanced packaging (CoWoS, SoIC, InFO).
- $6.7B of customer prepayments collected in six months.
- Nvidia advance payments cited inside long-term supply agreements.
- Rising 12-inch-equivalent wafer ASP as leading-edge mix grew.
- 2021 platform mix: smartphone 44%, HPC 37%; HPC already the largest absolute-dollar growth sector.
The 2022 article was right because it understood capex as strategy, not just accounting. The 2026 update has to ask the harder question: what does that strategy now buy.
Section 02 From foundry gauntlet to AI industrial plan
In 2022, the capex story was mostly framed as TSMC versus Intel versus Samsung. In 2026, the story is bigger. TSMC's capex is the physical layer behind AI infrastructure: leading-edge logic for AI accelerators and server CPUs, networking chips, HBM integration, CoWoS and SoIC packaging, and a global fab footprint that exists to make those workloads producible at scale.
The contest moved from foundry bragging rights to AI industrial capacity. TSMC's capex is no longer just a foundry fight. It is the construction crew for the AI economy.
Section 03 The 2026 capex number
TSMC's 2025 Form 20-F reports capital expenditures of US$40.895B in 2025 and 2026 capex expected between US$52B and US$56B, with the filing noting that the budget can be adjusted by market conditions and is mainly focused on manufacturing capacity and technology upgrades that support customer fabrication and technology needs[2].
The number is huge. The mix is the story.
The 2026 number is bigger than the 2022 "gauntlet." But the more important question is not size alone. It is what the spending is buying.
Section 04 HPC became the center of gravity
The platform mix tells the AI story directly. TSMC's 2025 Form 20-F shows HPC revenue of NT$2.193T, 58% of 2025 net revenue, up from 43% in 2023 and 51% in 2024, with HPC growth of 48% year over year. Smartphone revenue is 29% of 2025 net revenue. TSMC describes HPC as driven by data explosion and AI application innovation and defines the platform to include AI GPUs, AI ASICs, CPUs, server processors, and high-speed networking chips[2].
TSMC used to be understood through the iPhone cycle. Now it is increasingly understood through the AI/HPC buildout.
Apple still matters. But the center of gravity has moved. TSMC's capex is now tied to the demands of AI infrastructure customers as much as to the mobile cycle that defined the 2010s.
Section 05 Advanced nodes are where the value concentrates
The wafer revenue mix concentrates the spend. TSMC's 2025 Form 20-F reports 3 nm at 24% of 2025 wafer revenue, 5 nm at 36%, and 7 nm at 14%, with 7 nm and below totaling 74% of wafer revenue, up from 69% in 2024[2].
TSMC's capex is not generic semiconductor capacity. It is concentrated around high-value advanced nodes because AI accelerators and HPC chips need the best power, performance, and density. That pushes capex toward 2 nm, 3 nm, and the supporting ecosystem that turns those nodes into shipping products. The capex is concentrated where AI value is accumulating.
Section 06 CoWoS and SoIC turned packaging into capex strategy
TSMC's 2026 Technology Symposium frames packaging as a first-class capex item. TSMC is producing 5.5-reticle-size CoWoS, plans 14-reticle-size CoWoS in 2028 (around 10 large compute dies and 20 HBM stacks), and expects expansion beyond 14 reticles in 2029. A14-to-A14 SoIC is planned for production availability in 2029 at 1.8x higher die-to-die IO density than N2-on-N2 SoIC. COUPE co-packaged optics on substrate begins production in 2026 with 2x power efficiency and 10x latency reduction versus pluggable board versions[3].
Capex is no longer just fab shells and EUV tools. AI compute needs package-scale integration. CoWoS, SoIC, and co-packaged optics are now part of the foundry capex roadmap. AI scaling moved from wafer starts into package-scale systems.
Section 07 ASML shows the upstream pull
ASML's Q4 2025 results reported Q4 net bookings of EUR 13.2B, EUV bookings of EUR 7.4B, 2025 total net sales of EUR 32.7B, and a year-end backlog of EUR 38.8B, with 2026 net sales guidance of EUR 34B to EUR 39B and customer commentary that capacity plans had become more positive due to sustainable AI-related demand[4].
TSMC capex does not happen in isolation. EUV scanners, deposition tools, etch tools, metrology, inspection, advanced packaging tools, and test systems all sit upstream. AI demand pulls the whole tool ecosystem forward. The AI capex wave begins in hyperscaler budgets, flows through Nvidia and custom ASICs, then lands in TSMC fabs and ASML order books.
Section 08 The capex flywheel
The reason TSMC's capex compounds is that the spending becomes more than buildings and tools. It becomes process maturity, which becomes customer trust, which becomes the next round of demand. The flywheel is what turns capital into a moat.
AI/HPC demand
Customer commitments
Capex
Advanced-node capacity
Yield learning
PDK maturity
CoWoS & SoIC
Customer trust
More demand
TSMC's advantage compounds because spending becomes process maturity, which becomes customer trust, which becomes more leading-edge demand. Intel and Samsung can spend money, but they have to prove yield, customer trust, and ecosystem maturity at the same time. Capex compounds only when it becomes customer confidence.
Section 09 Intel is the serious counterpoint
Intel is not irrelevant. Intel's newsroom confirms that Panther Lake is the first client SoC built on Intel 18A and has entered production, that Fab 52 in Arizona is fully operational and set to reach high-volume production on 18A, and that Clearwater Forest is Intel's first 18A server processor expected in the first half of 2026, with 18A using RibbonFET and PowerVia[5].
Intel is trying to prove that it can turn capex into competitive internal manufacturing again. The 18A story is the real counterpoint to TSMC's dominance. But the burden is high because product teams and external customers need to trust the node, yield, PDKs, packaging, and supply chain at the same time. Intel's challenge is not announcing a node. It is earning manufacturing trust again.
Section 10 Samsung is also fighting the same battle
Samsung's FY2025 results describe a foundry business that began mass production of first-generation 2 nm products, began shipments of 4 nm HBM base-die products in Q4 2025, and plans 2026 foundry growth focused on ramping second-generation 2 nm products. Samsung said it would strengthen competitiveness through integrated solutions combining logic, memory, and advanced packaging[6].
Samsung is important because it combines memory, logic, and packaging under one roof. That vertical integration is strategically valuable. But foundry trust still depends on yield, roadmap execution, and customer wins. Samsung has the right assets. The test is whether it can convert them into trusted leading-edge foundry share.
Intel 18A and Panther Lake
- Panther Lake as the first client SoC on 18A; already in production.
- RibbonFET and PowerVia (GAA + backside power delivery).
- Fab 52 in Arizona fully operational on 18A.
- Clearwater Forest as the first 18A server CPU, expected H1 2026.
- Burden: external-customer trust, not just internal product success.
Samsung 2 nm & logic+memory+packaging
- Mass production of first-generation 2 nm products.
- 4 nm HBM base-die shipments starting Q4 2025.
- 2026 focus on second-generation 2 nm ramp.
- Integrated logic, memory, and advanced-packaging solutions.
- Burden: convert vertical integration into trusted leading-edge foundry share.
Section 11 The real race is trusted capacity
Capex alone does not win. Customers need yield, cycle time, PDK maturity, IP ecosystem, EDA readiness, advanced packaging, stable roadmap, predictable capacity, strong customer support, and a track record of proven high-volume ramps. TSMC's advantage is that customers believe its capex will become usable capacity. That belief is the moat.
The foundry race is no longer about who spends the most. It is about whose spending customers trust.
Section 12 What people get wrong about TSMC capex
The weak interpretation in 2026 is that TSMC is spending more than Intel and Samsung. The better interpretation is that TSMC is turning AI demand into the manufacturing base for the next compute platform. The spending is not just defensive. It is customer-backed. It is concentrated on advanced nodes and advanced packaging. It is tied to AI/HPC demand. And it reinforces the PDK, yield, and customer-trust flywheel. TSMC's capex is strategy written in concrete, EUV tools, and CoWoS lines.
$40B-$44B gauntlet
- Capex jumped from $30B-$35B expectation to $40B-$44B plan.
- 70%-80% of capex directed to 7 nm / 5 nm / 3 nm / 2 nm.
- $6.7B of customer prepayments collected in six months.
- Framed as Intel and Samsung struggling to keep up at scale.
- 2021 platform mix: smartphone 44%, HPC 37%.
$52B-$56B industrial plan
- 2025 capex US$40.895B; 2026 plan US$52B-$56B.
- HPC 58% of 2025 net revenue; smartphones 29%.
- 7 nm and below at 74% of wafer revenue (3 nm 24%, 5 nm 36%, 7 nm 14%).
- 5.5-reticle CoWoS today, 14-reticle CoWoS by 2028.
- ASML EUV backlog and 2026 sales guide pulled by AI demand.
Smartphone 44%, HPC 37% in TSMC platform mix
HPC already called the largest absolute-dollar growth sector even before the AI capex cycle accelerated[1].
TSMC announces $40B-$44B capex plan
Raised from a $30B-$35B prior expectation; framed as a foundry gauntlet against Intel and Samsung[1].
70%-80% of capex directed to 7 nm / 5 nm / 3 nm / 2 nm
Roughly 10% to masks and advanced packaging including CoWoS, SoIC and InFO[1].
TSMC capex reaches US$40.895B
Form 20-F reports 2025 capital expenditures of US$40.895B, mainly focused on advanced-node capacity and technology upgrades[2].
HPC reaches 58% of revenue
HPC revenue NT$2.193T, +48% YoY; smartphone 29%; HPC defined to include AI GPUs, AI ASICs, CPUs, server processors, and networking chips[2].
7 nm and below at 74% of wafer revenue
3 nm 24%, 5 nm 36%, 7 nm 14%; up from 69% at 7 nm and below in 2024[2].
TSMC plans US$52B-$56B capex
2026 plan focused on manufacturing capacity and technology upgrades supporting customer fabrication needs[2].
ASML reports major EUV bookings and backlog
Q4 net bookings EUR 13.2B, EUV EUR 7.4B, 2025 sales EUR 32.7B, backlog EUR 38.8B, 2026 sales guide EUR 34-39B, AI-driven demand[4].
TSMC produces 5.5-reticle CoWoS
Packaging-as-allocation layer firmly established; COUPE co-packaged optics also begins production in 2026[3].
14-reticle CoWoS target
Around 10 large compute dies and 20 HBM stacks per package by the end of the decade[3].
A14-to-A14 SoIC and beyond-14-reticle packaging
SoIC at 1.8x higher die-to-die IO density vs N2-on-N2; CoWoS expected to extend further[3].
Section 13 Risks and limits
The capex-as-industrial-plan reading rests on TSMC filings, ASML results, and Intel and Samsung company materials. It is worth being explicit about where the case can break.
Capex forecasts can change depending on market conditions; the 2026 plan is a range, not a guarantee.
AI demand may not grow smoothly; capex commitments are durable but demand cycles are not.
Customer concentration increases revenue and roadmap risk for the foundry.
TSMC's Form 20-F does not name every major customer in platform or customer concentration tables; specific shares should not be inferred.
Advanced packaging capacity is not the same as final AI accelerator output; CoWoS, HBM, substrates, power, thermal, assembly and test are separate bottlenecks.
Intel 18A could improve Intel's manufacturing credibility if execution is strong; dependency is not one-way.
Samsung can still compete where memory, logic and packaging integration matter together.
Geopolitical risk around Taiwan remains material to any TSMC-centric thesis.
TSMC technology symposium roadmap targets are not guaranteed capacity outcomes.
This essay is industry analysis, not investment advice; cycle and customer dynamics can move quickly.
The point is not that TSMC can spend its way around every risk. The point is that AI has made TSMC's capex one of the clearest maps of where compute scarcity is moving.
Section 14 Final verdict
The 2022 article was right. TSMC's $40B to $44B capex plan was a gauntlet. The 2026 version is larger: TSMC's capex is now the industrial plan behind AI compute, concentrated on 2 nm, 3 nm, CoWoS, SoIC, advanced packaging, yield learning, PDK maturity, global manufacturing capacity, and HPC customer trust.
Intel and Samsung still matter. But the foundry race is no longer won by roadmap slides. It is won by converting capital into trusted capacity.
The AI boom is not only being trained in data centers. It is being poured into TSMC's capex budget.
Section 15 Evidence ledger and source notes
| Source | Claim | Why it matters |
|---|---|---|
| SemiAnalysis (2022) | $40B-$44B 2022 capex plan; 70%-80% to 7/5/3/2 nm; 10% to masks and advanced packaging; $6.7B prepayments; smartphone 44% / HPC 37% in 2021 mix. | Anchors the historical capex framework. |
| TSMC 2025 Form 20-F | 2025 capex US$40.895B; 2026 plan US$52-56B; HPC 58% of revenue (+48% YoY); 7 nm and below 74% of wafer revenue; 3 nm 24%, 5 nm 36%, 7 nm 14%. | Quantifies the shift to AI/HPC and advanced-node concentration. |
| TSMC 2026 Symposium | 5.5-reticle CoWoS today; 14-reticle CoWoS by 2028 with ~10 dies + 20 HBM; A14-A14 SoIC 2029; COUPE in 2026. | Packaging-as-capex strategy. |
| ASML Q4 2025 | Q4 bookings EUR 13.2B; EUV EUR 7.4B; 2025 sales EUR 32.7B; backlog EUR 38.8B; 2026 guide EUR 34-39B; AI-driven medium-term plans. | Upstream equipment confirmation of the same pull. |
| Intel Newsroom | Panther Lake first 18A client SoC in production; Fab 52 fully operational on 18A; Clearwater Forest H1 2026 first 18A server CPU. | Counterpoint to TSMC's capex dominance. |
| Samsung FY2025 | Mass production of first-gen 2 nm; 4 nm HBM base-die shipments Q4 2025; 2026 focus on second-gen 2 nm; integrated logic+memory+packaging solutions. | Samsung's parallel push; vertical integration as its lever. |
Footnotes & sources
- SemiAnalysis, “TSMC Throws Down a $40B-$44B Gauntlet, Far Surpassing Intel And Samsung,” 2022 (PDF supplied by author). Source for the $40B-$44B 2022 capex plan, the 2021 $25B-$28B prior plan and ~$30B actual, the 2022 capex mix (70%-80% to 7 nm, 5 nm, 3 nm and 2 nm; ~10% to masks and advanced packaging including CoWoS, SoIC, InFO), the $6.7B six-month customer prepayments figure, the Nvidia advance-payment references inside long-term supply agreements, the rising 12-inch-equivalent wafer ASP framing, the 2021 platform mix of smartphone 44% and HPC 37%, and the framing of HPC as the largest absolute-dollar growth sector.
- TSMC, “2025 Form 20-F,” investor.tsmc.com/…/2025_20F Report. Source for 2025 capital expenditures of US$40.895B, the 2026 capex plan of US$52B-$56B, HPC at 58% of 2025 net revenue with NT$2.193T (+48% YoY), smartphones at 29%, HPC at 43% in 2023 and 51% in 2024, the HPC definition that includes AI GPUs, AI ASICs, CPUs, server processors and high-speed networking chips, and the wafer-revenue mix of 3 nm at 24%, 5 nm at 36%, 7 nm at 14%, with 7 nm and below at 74% of total wafer revenue.
- TSMC, “TSMC 2026 Technology Symposium,” pr.tsmc.com/english/news/3302. Source for 5.5-reticle CoWoS in production, 14-reticle CoWoS planned by 2028 with around 10 large compute dies and 20 HBM stacks, expansion beyond 14 reticles in 2029, A14-to-A14 SoIC production availability in 2029 at 1.8x higher die-to-die IO density vs N2-on-N2 SoIC, and COUPE co-packaged optics on substrate beginning production in 2026 with 2x power efficiency and 10x latency reduction vs pluggable versions.
- ASML, “Q4 2025 Financial Results,” asml.com/…/q4-2025-financial-results. Source for Q4 2025 net bookings of EUR 13.2B, EUV bookings of EUR 7.4B, 2025 total net sales of EUR 32.7B, the end-2025 backlog of EUR 38.8B, the 2026 net sales guidance range of EUR 34B to EUR 39B, and the customer commentary on a more positive medium-term view driven mainly by sustainable AI-related demand.
- Intel Newsroom, “Intel Unveils Panther Lake Architecture — First AI PC Platform Built on 18A,” newsroom.intel.com. Source for Panther Lake as the first client SoC built on Intel 18A and the production status, the fully operational Fab 52 in Arizona ramping to high-volume production on 18A, the framing of Clearwater Forest as the first 18A server processor expected in H1 2026, and the description of Intel 18A using RibbonFET and PowerVia.
- Samsung Newsroom, “Samsung Electronics Announces Fourth Quarter and FY 2025 Results,” news.samsung.com. Source for Samsung Foundry's mass production of first-generation 2 nm products, the Q4 2025 4 nm HBM base-die shipments, the 2026 focus on ramping second-generation 2 nm products, and the framing of strengthened competitiveness through integrated solutions combining logic, memory, and advanced packaging.