Veeco's Transformation: The Small Toolmaker Under AI's Biggest Hardware Bottlenecks EUV mask blanks Laser annealing HBM Advanced packaging GaN power Silicon photonics AI data storage Axcelis merger

Section 1  ·  Historical frameWhat the 2022 article got right

The 2022 SemiAnalysis piece, The Transformation of Veeco, described a small semiconductor capital equipment company carrying two difficult inheritances.^[1] Veeco had historically sold ion beam deposition and etch tools into hard-drive heads, a cyclical and increasingly mature market. It also had a major LED MOCVD business that had become structurally unattractive due to Chinese commodity competition. The 2022 read was that Veeco was repositioning around a better mix of semiconductor niches, and that the repositioning deserved attention even though the headline financials were not yet showing it.

The repositioning was not abstract. Veeco acquired Ultratech in 2017, which deepened its laser annealing and advanced packaging lithography capabilities. It exited the commodity LED equipment business in 2018. The narrative growth vectors were data storage, GaN power and RF, microLED, advanced packaging lithography, EUV mask blanks, and laser annealing for advanced nodes.^[1] The 2022 visuals carried the argument. The page 2 evolution slide showed Veeco moving from HDD ion beam tools and LED MOCVD toward laser annealing, advanced packaging lithography, and a broader strategy. The page 11 EUV mask diagram showed why EUV masks are different: anti-reflective coating on top, an absorber layer, ruthenium capping, a Mo/Si multilayer mirror, a low thermal expansion substrate underneath, and a conductive backside coating. The page 13 laser annealing slide explained that local laser exposure replaces full-wafer heating, allowing a lower thermal budget and less damage to fragile devices. The page 14 gate transistor evolution slide connected laser annealing demand to FinFET and gate-all-around transitions.^[1]

Four years later, that 2022 framing reads less like a forecast and more like a map of the niches Veeco actually moved into. The right way to update it is not to claim Veeco is now an AI company. It is to look at how the niches have aged in an AI manufacturing environment and where the company sits inside the bottlenecks that now constrain AI hardware production.

Section 2  ·  MixVeeco has become more semiconductor-heavy

Veeco's transformation should be judged by mix, not by total revenue. The 2025 full-year results show why. Total revenue was about US$664.3 million, down from 2024, with semiconductor revenue of about US$476.6 million, or roughly 72% of total revenue.^[2] Compound semiconductor and data storage segments were weaker than in 2024, which is the reason the headline revenue line did not look like a clean growth story. The center of gravity moved further toward semiconductor process equipment exactly as AI hardware manufacturing became more complex.

The weak version of the story is Veeco is booming because AI. The stronger version is that Veeco's center of gravity has shifted toward semiconductor process equipment exactly as AI hardware manufacturing becomes more complex.

That distinction matters because it tells you what to watch. Watching total revenue tells you about cyclical conditions inside compound semiconductor and data storage. Watching semiconductor segment revenue, and the specific applications underneath it, tells you about Veeco's exposure to the steps where AI hardware production is hardest to scale. Those two stories are different, and they will keep being different through the Axcelis combination.

Section 3  ·  Laser annealingThe clearest advanced-node story

Advanced chips need thermal processing. They need heat to activate dopants, to drive diffusion, and to repair the damage that earlier process steps leave behind. The catch is that as devices become smaller, more vertical, and more fragile, the thermal budget gets tighter. Traditional full-wafer heating risks damaging sensitive structures or causing diffusion in places that need to stay sharp. Laser annealing solves that problem by heating local regions for very short periods, often nanoseconds, leaving the rest of the wafer cold.

The 2022 article connected laser annealing demand to gate-all-around transitions and dopant activation in advanced devices.^[1] Veeco's current investor materials extend that argument. The company describes its Laser Spike Annealing as a production tool of record at multiple Tier 1 logic customers and at an HBM DRAM customer, and is positioning a Nanosecond Annealing platform aimed at future logic and memory applications.^[4] Veeco's 2025 Annual Report supports the same framing with a more conservative tone, describing laser annealing as one of the company's strategic process technologies inside the semiconductor segment.^[3]

As chips become denser, more vertical, and more fragile, the ability to heat only what needs heating becomes more valuable.

Section 4  ·  EUV mask blanksThe hidden lithography layer

Everyone talks about ASML when discussing EUV lithography. That is correct, but incomplete. EUV scanners cannot pattern anything without an EUV mask, and EUV masks are not normal transmissive masks. They are reflective multilayer mirrors built on low thermal expansion substrates. The stack matters. So does the company that lays down the multilayer film.

The 2022 article explained that Veeco's ion beam deposition tools are used for Mo/Si multilayer deposition and ruthenium capping in EUV mask blank manufacturing.^[1] Veeco's 2025 Annual Report and investor presentation continue that role, describing NEXUS ion beam deposition systems as used in EUV mask blank manufacturing, with the company framing itself as the production tool of record in that step.^[3][4] ASML's own scale shows how important the EUV ecosystem has become. The 2025 ASML annual report disclosed substantial High-NA progress, large backlog, and meaningful EUV investment.^[5] Veeco sits in the less visible mask blank layer of that ecosystem.

ASML gets the spotlight, but EUV cannot scale without the mask blank ecosystem. Veeco sits in that hidden layer.

Section 5  ·  PackagingAdvanced packaging is central because AI is packaging-limited

AI accelerators are no longer limited only by transistor scaling. They are limited by memory bandwidth, interconnect density, package size, thermal constraints, and HBM integration. That is why advanced packaging has moved from a back-end detail to a core scaling layer. TSMC's 2025 annual reporting discusses CoWoS, InFO, SoIC and COUPE as part of its 3D Fabric platform, with CoWoS integrating SoCs and HBM stacks for HPC and AI applications.^[6]

The 2022 article connected Veeco's advanced packaging lithography to copper pillars, TSVs, Foveros, InFO, CoWoS, FoCoS, HBM, and related packaging flows.^[1] Four years later, that connection is stronger, not weaker. Veeco's 2025 Annual Report and 2026 investor presentation describe wet processing and lithography tools positioned at 2.5D and 3D packaging, including process steps tied to AI accelerator and HBM packaging.^[3][4]

AI chips are no longer limited only by transistor scaling. They are limited by memory bandwidth, interconnect density, packaging capacity, and thermal constraints.

Section 6  ·  HBMWhere Veeco gets a stronger AI connection

HBM is one of the clearest AI hardware bottlenecks. Each generation of AI accelerator pulls harder on HBM capacity, DRAM process complexity, advanced packaging integration, and the wet processing steps in between. Nvidia's Q1 FY2027 print, with US$81.6 billion in revenue and data center as the dominant driver of growth, is the most visible signal of how concentrated that pull has become.^[7]

Veeco should not be described as the main HBM beneficiary. SK hynix, Micron, and Samsung are the memory beneficiaries, with TSMC capturing the advanced packaging integration value through CoWoS and adjacent platforms.^[6] The accurate claim is narrower. Veeco sells into the process steps that become more important as HBM and 3D packaging scale: ion beam deposition for select interconnect layers, laser annealing for DRAM and HBM-related thermal steps, and wet processing for the packaging side. The 2026 investor presentation explicitly references HBM DRAM customer evaluation for advanced annealing.^[4]

Veeco is not the primary HBM winner. But it sells into process steps that become more important as HBM and 3D packaging scale.

Section 7  ·  Compound semiThe optionality layer

Compound semiconductor is strategically interesting and financially uneven. Veeco's 2025 results show compound semiconductor revenue down year over year, so the segment is not a smooth growth engine right now.^[2] The strategic case rests on a different set of variables. AI data centers are becoming power-constrained and connectivity-constrained, which gives GaN power and silicon photonics long-term relevance. Veeco's Propel 300mm GaN-on-silicon and Lumina+ arsenide and phosphide platforms are positioned at GaN power, RF, microLED, and photonics applications across automotive, communications, and AI infrastructure.^[3][4]

The honest framing is that compound semiconductor is not yet the smooth growth engine. It is the optionality layer. If GaN power adoption accelerates, if photonics and co-packaged optics move beyond pilot lines, if microLED gets a credible volume use case, the segment's revenue profile changes. None of those outcomes is guaranteed on a 12-month view.

Compound semiconductor is not yet the smooth growth engine. It is the optionality layer.

Section 8  ·  StorageAI-adjacent, but cyclical

The 2022 article argued that hard-drive tooling could benefit from data center demand, more magnetic heads per drive, more platters per drive, and more complex drive architectures.^[1] That narrative is still partially true. AI and cloud workloads pull on storage at scale, and HAMR adoption increases manufacturing complexity, which usually helps tool vendors.

The numbers are less generous. Veeco's data storage revenue fell sharply year over year in 2025, which means data storage is not the main Veeco transformation story today.^[2] The fair read is that data storage is an AI-adjacent cyclical kicker, not the core thesis. If HDD makers add more heads per drive, transition further into HAMR, and add platters, Veeco's tool demand can rebound. None of that is guaranteed on the same timeline as the AI accelerator buildout.

Data storage is an AI-adjacent cyclical kicker, not the core thesis.

Section 9  ·  ScaleThe Axcelis merger changes the endgame

Veeco is not just transforming on its own. Axcelis and Veeco announced an all-stock merger in 2025, with the combined company framed as a larger US wafer fabrication equipment platform.^[8] The merger SEC exhibit and investor release describe a combined enterprise value of approximately US$4.4 billion, pro forma fiscal 2024 revenue of about US$1.7 billion, and Veeco shareholders expected to own about 42% of the combined company, with the combined portfolio spanning ion implantation, laser annealing, ion beam deposition, advanced packaging solutions, MOCVD, and wet processing.^[9]

Scale matters in semiconductor equipment in ways that revenue alone does not capture. Customers reward global support depth, multi-tool process recipes, R&D breadth, customer-facing PDK and integration support, and credibility through multiple node ramps. A merged Axcelis-Veeco does not become Applied Materials, Lam Research, or Tokyo Electron in size, but it does become a more credible mid-tier US wafer fabrication equipment supplier with a portfolio that touches several AI hardware bottlenecks simultaneously.

The Axcelis deal turns Veeco's transformation from a niche turnaround into a scale story.

Section 10  ·  EvidenceEvidence ledger

Section 11  ·  ScorecardSegment scorecard

Section 12  ·  Risk registerRisks and limitations

This essay is an analysis of public disclosures and historical context. It is not investment advice. The honest risks against the read above run in several directions. They are listed here so the conclusions can be stress-tested.

Section 13  ·  Bottom lineBottom line

Section 14  ·  DefinitionsGlossary

Section 15  ·  MethodSources and method notes