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Essay No. 022 · AI Infrastructure · Melbourne, Australia

AI Infrastructure Silicon Photonics Optical I/O Co-Packaged Optics Intel Nvidia Broadcom TSMC COUPE Data Centers Networking AI Factories

When AI Runs Out of Copper.Original analysisNot investment advice

Why optical I/O and co-packaged photonics are becoming the next AI infrastructure bottleneck.

Pugalenthi Magendran

March 2026 · Melbourne, Australia

12 min read

AI scaling is usually described through GPUs, HBM, and data centers. But the next bottleneck may be data movement. As AI factories scale across racks, clusters, and campuses, copper interconnect starts to hit power, reach, and density limits. The race to replace copper with light has begun.

The AI conversation is usually about compute. How many GPUs. How much HBM. How many tokens. How many megawatts. How many data centers. Compute without movement is useless. Every AI system is also a data-movement machine. Model weights move. Activations move. Gradients move. KV cache moves. Training data moves. Inference requests move. GPUs exchange intermediate results across links, switches, racks, and sometimes entire campuses.

At small scale, copper is good enough. At AI factory scale, copper starts to become the bottleneck. Copper links lose signal. They burn power. They need retimers. They get bulky. They struggle with reach. They make every extra rack more expensive to connect.

In 2021, Intel’s silicon photonics thesis looked like a strange foundry angle. Intel was struggling in leading-edge logic, but the uploaded SemiAnalysis piece argued that Intel had a hidden wedge: co-packaged silicon photonics. If future data centers ran into copper I/O limits, Intel’s photonics and packaging experience could become strategically valuable.¹

That idea has aged well. The market changed. In 2026, this is no longer only an Intel story. Nvidia has announced co-packaged optics switches for AI factories. Broadcom has delivered CPO Ethernet switches. TSMC is building COUPE as a neutral photonics integration platform. Ayar Labs and Alchip are pushing optical I/O directly toward AI accelerators.

The AI factory is starting to run out of copper.

Key idea

The correct claim is not that Intel wins foundry because it has photonics. The correct claim is that AI systems are running into a data-movement wall, and optical I/O is becoming a strategic layer of the AI factory. Intel saw this early and still has real photonics credibility, but the 2026 race is ecosystem-wide.

I. The 2021 thesis

In June 2021, Dylan Patel published a SemiAnalysis piece arguing that Intel’s IDM 2.0 foundry pitch was hard. TSMC was the trusted neutral foundry. Intel had process delays and customer-conflict issues at leading-edge logic. The stronger wedge was silicon photonics. Intel had years of high-volume photonics manufacturing experience and the packaging credibility to back it up. If data movement kept growing faster than compute, and copper electrical signaling hit its scaling limits, Intel’s photonics could become a Trojan horse into future data-center silicon.¹

I revisited that piece because the bottleneck argument turned out to be exactly right. The Intel-exclusive framing did not.

2021 thesis

Intel may struggle to win foundry customers on logic alone. But if the data center hits copper I/O limits, Intel’s silicon photonics and packaging capabilities could become a Trojan horse into future AI and data-center silicon.

II. AI is a data-movement problem

The reason copper matters is mechanical. AI workloads are dominated by moving data, not only by computing on it.

Diagram 01 · AI data-movement surface

Weights

Loaded onto accelerators each iteration.

Activations

Streamed between layers and devices.

Gradients

Synchronised across GPUs during training.

Optimizer state

Distributed across the cluster.

KV cache

Grows with context window during inference.

Embeddings

Retrieved from vector stores at inference.

Rack & cluster

East-west traffic between accelerators.

Campus

Long-reach links across buildings.

ASML’s 2025 strategic report frames AI as requiring leading-edge logic and significantly more DRAM than traditional compute. Every one of these data paths is part of the same problem.¹¹

The AI factory is only as fast as its slowest data path.

III. Why copper starts to break

Copper is excellent for short distances. It is cheap, mature, reliable, and everywhere. It gets harder as bandwidth and distance rise. Signal attenuation grows. Crosstalk grows. Cables get bulky. Reach shrinks. Retimers consume more power. Routing congestion compounds.

Diagram 02 · The copper pressure cascade

More accelerators per AI factory

More aggregate bandwidth required

More copper cables and retimers

More electrical signaling power and heat

More routing congestion and shorter reach

Copper hits power, reach, and density limits

Copper does not disappear overnight. The highest-bandwidth links move optical first.

Copper remains the default until the cost of keeping it becomes higher than the cost of replacing it.

IV. Intel saw the problem early

Intel demonstrated an Optical Compute Interconnect (OCI) chiplet co-packaged with an Intel CPU at OFC 2024. Intel says the first implementation supports up to 4 Tbps bidirectional transfer using 64 channels of 32 Gbps in each direction, runs over up to 100 m of fiber, and consumes about 5 pJ/bit compared with about 15 pJ/bit for pluggable optical transceiver modules. Intel positions the technology for AI infrastructure, HPC, CPU/GPU cluster connectivity, coherent memory expansion, and resource disaggregation.²³

Card · Intel OCI chiplet at a glance

4 Tbps

Bidirectional transfer per chiplet

64 × 32 Gbps

Channels per direction

100 m

Fiber reach

5 pJ/bit

Energy per bit vs ~15 pJ/bit for pluggables

Intel says OCI targets AI/HPC clusters, CPU-GPU connectivity, coherent memory expansion, and resource disaggregation.²

Intel may not win the whole foundry war with photonics, but it does have a real technology asset.

V. Why the “only Intel” thesis is weaker now

The 2021 piece’s Intel-specific framing needs updating. By 2026 the photonics ecosystem is wide. Nvidia has photonics switch products. Broadcom has shipped CPO. TSMC has built COUPE as an integration platform. Ayar Labs and Alchip are building optical I/O around TSMC packaging. Jabil took over Intel’s pluggable transceiver product line so Intel could refocus on the strategic layer.

2021 framing

Intel-as-photonics-Trojan-horse

Implicit assumption · Intel was the only credible high-volume silicon photonics player.
TSMC silent · not seen as a photonics integration platform.
Nvidia silent · networking framed mostly as InfiniBand / Ethernet over copper or pluggables.
Broadcom silent · CPO at switches not yet a public product line.

2026 reality

Ecosystem-wide race

Intel · OCI chiplet at 5 pJ/bit, real but no longer alone.²
Nvidia · Spectrum-X and Quantum-X Photonics CPO switches.⁴
Broadcom · Bailly 51.2 Tbps CPO Ethernet switch shipping.⁵
TSMC · COUPE photonic engine on substrate, production targets in 2026.⁶⁷
Ayar Labs + Alchip · optical I/O for AI accelerators on the TSMC stack.⁹
Jabil · absorbed Intel pluggable transceivers, letting Intel refocus.¹⁰

Intel’s edge is experience. TSMC’s edge is ecosystem gravity. Nvidia’s edge is the AI factory platform.

VI. Nvidia made photonics mainstream

Nvidia announced Spectrum-X Photonics and Quantum-X Photonics as co-packaged optics networking switches designed to scale AI factories to millions of GPUs. Nvidia claims 3.5x power efficiency, 63x signal integrity, 10x network resiliency, and 1.3x faster deployment compared with traditional approaches, with Spectrum-X Photonics configurations reaching 100 Tbps and 400 Tbps total bandwidth and Quantum-X Photonics providing 144 ports of 800 Gb/s InfiniBand, with Quantum-X arriving later in 2025 and Spectrum-X Ethernet switches in 2026.⁴

When Nvidia puts photonics into the AI factory roadmap, photonics stops being an exotic Intel story and becomes mainstream AI infrastructure.

Intel identified the optical I/O bottleneck early. Nvidia turned it into an AI factory product category.

VII. Broadcom shows CPO is real networking infrastructure

Broadcom delivered Bailly, described as the industry’s first 51.2 Tbps co-packaged optics Ethernet switch platform. It integrates eight silicon-photonics-based 6.4 Tbps optical engines around Broadcom’s Tomahawk 5 switch chip and targets large-scale AI clusters.⁵

Networking switches are the natural first home for CPO because they are I/O-heavy and sit at the centre of AI clusters. Power and density pain show up there first.

CPO comes to switches first because switches are where copper pain becomes impossible to ignore.

VIII. TSMC wants the ecosystem layer

TSMC is building Compact Universal Photonic Engine, COUPE, as an integration platform for the rest of the ecosystem. TSMC frames COUPE around SoIC-X chip stacking that places an electrical die on top of a photonic die, lowering impedance at the die-to-die interface and improving energy efficiency. TSMC’s 2026 North America Technology Symposium says true co-packaged optics using COUPE on substrate begins production in 2026, with claims of 2x power efficiency and 10x latency reduction versus a pluggable version on the circuit board.⁶⁷⁸

If TSMC becomes the neutral optical I/O integration platform, Intel’s photonics advantage becomes less of a Trojan horse and more of one option in a broader ecosystem.

IX. Ayar Labs and Alchip show the TSMC path

Ayar Labs and Alchip jointly unveiled a co-packaged optics solution for AI data-center scale-up built on TSMC’s COUPE, SoIC, and advanced process technologies. The two companies claim more than 100 Tbps of scale-up bandwidth per accelerator and more than 256 optical scale-up ports per device, aimed at multi-rack AI scale-up where copper reach starts to fail.⁹

The interesting part is not the laser. The interesting part is the integration recipe: optical engines, electrical die, advanced packaging, and customer-specific silicon, all stitched together on a shared foundry stack.

The winner will not simply be whoever makes the best photonic device. The winner will be whoever makes photonics easy to integrate into real AI systems.

X. The strategic market is optical I/O, not pluggable modules

The Jabil deal sharpened the picture. Jabil took over Intel’s silicon-photonics-based pluggable optical transceiver product lines, with Intel framing the move as a refocus toward silicon photonics components for existing markets and emerging applications.¹⁰

The implication is straightforward. Pluggables sit at the edge of the board, are increasingly commoditised, and serve a different market dynamic than the layer Intel cares about. CPO moves optics closer to the ASIC. Optical I/O moves the strategic question into the package itself. That is the part of the stack Intel and the rest of the photonics ecosystem are now competing on.

The question is not whether Intel can sell more pluggable modules. The question is whether Intel can help future CPUs, GPUs, switches, and AI accelerators move data optically at package scale.

XI. The new AI interconnect stack

Optical I/O does not arrive at every layer at once. The economics make sense at the high-bandwidth, high-distance edges first, then push inward over time.

Diagram 03 · The new AI interconnect stack

Campus / metro fabric

Optical now

Cluster-level network & switches

CPO frontier

Rack-to-rack links

Hybrid

Accelerator scale-up (optical I/O)

Emerging

Board-level links

Copper today

Package-level links & HBM

Copper / TSV

On-chip interconnect

Copper

Copper still dominates inside the package. Optics is winning at switches and long-reach scale-up. The middle layers are the contested ground.

XII. Why this matters for Intel Foundry

This is not a simple Intel bull case. Intel still has customer-trust issues, process execution risk, cost-structure pressure, and the structural problem of competing with potential foundry customers. TSMC’s neutrality remains a real advantage.

The photonics opportunity is still real. Intel’s OCI chiplet is a credible technology. Intel’s packaging experience is a credible asset. Intel’s U.S. and Western supply-chain positioning matters for some customers. Semi-custom integration around optical I/O is a plausible wedge. None of that guarantees commercial wins.

Diagram 04 · Photonics positioning map

Intel

Experience

Deep silicon photonics history, high-volume manufacturing, OCI chiplet credibility, U.S. supply-chain position. Still has to convert technology into foundry wins.²³

TSMC

Ecosystem gravity

COUPE, SoIC, and CoWoS form a neutral foundry stack the rest of the photonics ecosystem can build on. Production targets in 2026.⁶⁷

Nvidia

AI factory platform

Spectrum-X / Quantum-X Photonics CPO switches integrated into the rack-scale AI factory narrative.⁴

Three players, three edges. None of them wins this alone.

Photonics gives Intel a door. It does not guarantee customers walk through it.

Quick terms

XIII. What could break the thesis

A serious piece needs counterarguments. The optical I/O thesis has plausible failure modes.

Risks & counterarguments

Copper extension. Linear pluggable optics, smarter retimers, and better PCB materials may keep copper viable longer than expected.
CPO serviceability. Replacing a co-packaged optical engine is harder than swapping a pluggable. Operational risk slows adoption.
Thermal stress. Hot ASIC neighbours degrade laser reliability and detector performance.
Optical alignment yield. Sub-micron alignment tolerance compounds packaging cost.
Laser reliability. Mean time to failure for in-package lasers must improve to match data-center standards.
Standards fragmentation. UCIe, OIF, and Ethernet roadmaps may diverge in ways that slow ecosystem investment.
Nvidia vertical integration. If Nvidia keeps photonics largely in-house, the merchant photonics opportunity narrows.
TSMC gravity. A neutral COUPE platform could capture more of the integration market than Intel.
Intel execution. Strong technology does not equal commercial wins. Intel still has to land foundry customers.
Switch-only adoption. Broadcom may dominate switch CPO before optical I/O reaches processors at scale.
Software offload. Better compression, scheduling, and network architecture could reduce bandwidth pressure.

Optical I/O is likely real. Intel’s exclusive Trojan horse is less certain.

XIV. What to watch

Working checklist, not a prediction. Some of these signals will move first.

What to watch

Nvidia Spectrum-X / Quantum-X Photonics deployment milestones.
Broadcom Bailly CPO switch adoption beyond pilots.
TSMC COUPE on-substrate production ramp.
Ayar Labs and Alchip customer traction.
Intel OCI customer announcements outside its own CPUs.
CPO reliability and serviceability data from large operators.
Power per bit versus pluggable modules across generations.
Switch bandwidth roadmaps at 51.2 Tbps and 102.4 Tbps.
1.6T and 3.2T optical module adoption.
AI cluster size growth and scale-up architectures.
Accelerator-level optical I/O roadmaps.
HBM bandwidth versus network bandwidth gap.
Data-center power constraints and grid signals.
Standards: UCIe, OIF, Ethernet, InfiniBand-related developments.

XV. The optical I/O war

The next AI bottleneck may not be arithmetic. It may be movement.

GPUs can keep getting faster. HBM can keep getting denser. Data centers can keep getting larger. But if data cannot move efficiently across packages, racks, and AI factories, the system stalls.

Intel saw the optical I/O problem early. Nvidia made it mainstream. Broadcom shipped it into switches. TSMC is building the ecosystem. Ayar Labs and Alchip are pushing optical I/O toward accelerators.

The AI factory is starting to run out of copper. The race to replace it with light has begun.

¹ Patel, D. (Jun 2021). Intel’s Trojan Horse into the Foundry Business | Co-packaged Silicon Photonics is Intel’s Path Forward for IDM 2.0. SemiAnalysis. Historical anchor for the Intel-photonics-Trojan-horse thesis, including the IDM 2.0 framing and the copper-I/O bottleneck argument. Used as inspiration only. No content, structure, or charts reproduced.

² Intel (Jun 2024). Intel unveils first integrated optical I/O chiplet. OCI chiplet co-packaged with an Intel CPU, 4 Tbps bidirectional, 64 channels of 32 Gbps per direction, up to 100 m fiber, ~5 pJ/bit versus ~15 pJ/bit for pluggables, targeting AI infrastructure, HPC, CPU-GPU connectivity, coherent memory expansion, and resource disaggregation.

³ Intel. Silicon Photonics. Intel silicon photonics platform context including high-volume photonics manufacturing and OCI roadmap framing.

⁴ Nvidia (2025). Nvidia announces Spectrum-X Photonics co-packaged optics networking switches. Spectrum-X and Quantum-X Photonics CPO switches designed to scale AI factories to millions of GPUs, with claims of 3.5x power efficiency, 63x signal integrity, 10x network resiliency, and 1.3x faster deployment versus traditional approaches, including 100 Tbps and 400 Tbps configurations and 144 ports of 800 Gb/s InfiniBand.

⁵ Broadcom. Broadcom delivers industry’s first 51.2 Tbps co-packaged optics. Bailly platform integrating eight silicon-photonics-based 6.4 Tbps optical engines around Broadcom’s Tomahawk 5 switch chip, targeting large-scale AI clusters.

⁶ TSMC. 2024 North America Technology Symposium briefing. COUPE framed as Compact Universal Photonic Engine using SoIC-X stacking of an electrical die on top of a photonic die, motivated by explosive AI data-transmission growth.

⁷ TSMC. 2026 North America Technology Symposium briefing. Co-packaged optics using COUPE on substrate beginning production in 2026, with claims of 2x power efficiency and 10x latency reduction versus pluggable versions on the circuit board.

⁸ TSMC Research. On-chip interconnect / COUPE research. Technical framing of EIC/PIC integration and photonic engine packaging.

⁹ Ayar Labs & Alchip. Alchip and Ayar Labs unveil co-packaged optics for AI data-center scale-up. Joint solution claiming more than 100 Tbps of scale-up bandwidth per accelerator and more than 256 optical scale-up ports per device, built on TSMC’s COUPE, SoIC, and advanced process technologies, aimed at multi-rack AI scale-up.

¹⁰ Jabil. Jabil invests in the future of AI with Intel silicon photonics transceiver deal. Jabil absorbing Intel’s silicon-photonics-based pluggable transceiver product lines, with Intel refocusing on silicon photonics components for existing markets and emerging applications.

¹¹ ASML (2025). 2025 Annual Report, strategic report section. AI requires leading-edge, high-performance processor chips and a significant increase in DRAM compared with traditional compute architectures, with advanced Logic and AI-related DRAM as structural drivers.

¹² TSMC. 2025 Annual Report. Robust AI-related demand, mild non-AI recovery, advanced-node and packaging investment as structural drivers.