The Foundry Toll Road.Original analysisNot investment advice
In 2021, the bear case was that slowing Moore’s Law would pressure TSMC’s margins. In 2026, AI proved the opposite. Customers are not paying for cheap transistors. They are paying for performance-per-watt, advanced packaging, HBM integration, yield, capacity, and trust.
In 2021, the TSMC bear case sounded clean.
Moore’s Law was slowing. Transistor cost scaling was weakening. Gross margins would compress. 5G was already halfway done. 3D packaging would dilute the value of monolithic leading-edge scaling. That was the Morgan Stanley argument as summarised at the time.1
The uploaded SemiAnalysis article from June 2021 said that was the wrong way to understand TSMC. TSMC was not just selling wafers by the transistor. It was selling access to the manufacturing layer that made Apple, AMD, Nvidia, Amazon, and the rest of the advanced computing world possible. Customers were not buying cheap transistors. They were buying performance, power efficiency, yield, capacity, packaging, and trust.1
In 2026, the verdict is clearer.
The margin collapse did not happen. The opposite happened.
TSMC became more important.
The correct thesis is not “TSMC is expensive, so margins must fall.” The correct thesis is that TSMC’s pricing power comes from being the trusted manufacturing layer for the most valuable compute systems in the world. As AI makes performance-per-watt, packaging, memory proximity, capacity, and yield more important, TSMC’s value expands beyond wafers into system-level manufacturing.
I. The 2021 thesis
In June 2021, Dylan Patel published a SemiAnalysis essay reacting to a Morgan Stanley downgrade of TSMC. The bank’s argument was structural: slower Moore’s Law, weaker cost-per-transistor scaling, 5G already maturing, and the rise of 3D packaging and chiplets, would all converge to pressure TSMC’s gross margin.1
The SemiAnalysis rebuttal argued that this framing misunderstood TSMC. Customers do not buy transistors. They buy products. A more expensive wafer is still attractive if the end system delivers more performance, lower power, longer battery life, or better data-center economics. Advanced packaging and chiplets do not dilute the value of leading-edge logic; they increase how much leading-edge silicon content can sit inside a single product, raising not lowering TSMC’s strategic weight. TSMC was framed as a technology innovator, not a generic capacity provider.1
I read the SemiAnalysis piece as historical anchor only. The 2026 version of this argument has to be told with 2026 evidence.
TSMC should not be analysed as a commodity wafer supplier. Its value comes from enabling the world’s most valuable chip designers to turn architecture into manufacturable, high-yield, high-performance silicon.
II. The margin collapse did not happen
Start with the simple test the 2021 thesis was supposed to fail. If TSMC’s pricing power was eroding, gross margins should compress over time and forward guidance should follow.
That is not what 2026 looks like.
TSMC reported first-quarter 2026 revenue of US$35.9B, with gross margin of 66.2%, operating margin of 58.1%, and net profit margin of 50.5%. Q2 2026 guidance was US$39.0B–40.2B in revenue with gross margin guidance of 65.5%–67.5%. Management framed 2026 full-year revenue growth at “close to mid-30s percent” in US-dollar terms.23
A company losing pricing power does not guide mid-60s gross margin into its most advanced capacity. That is the simplest empirical answer to the 2021 framing.
III. The customer mix shifted toward AI
TSMC’s Q1 2026 platform mix is the cleanest way to see this. HPC was 61% of first-quarter revenue, with smartphones at 26%, IoT at 6%, automotive at 4%, and digital consumer electronics at 1%.3 The TSMC 2025 Annual Report described AI-related demand as robust throughout 2025, with non-AI end markets only mildly recovering.4
The old TSMC story was heavily tied to Apple and smartphones. The new story is AI and HPC. Smartphone share has not collapsed; it has been overtaken.
The old semiconductor cycle was consumer-led. The new one is AI-led.
IV. Advanced nodes still matter
If advanced nodes were losing pricing power, you would expect the wafer-revenue mix to drift toward older, cheaper nodes as customers chase cost. The opposite is happening.
TSMC reported in its Q1 2026 results that advanced technologies at 7nm and below accounted for 74% of wafer revenue, with 3nm at 25%, 5nm at 36%, and 7nm at 13%.3
A more expensive wafer can still be the right choice if it delivers better performance per watt, higher throughput, lower latency, better die-area efficiency, lower system power, higher product ASP, or lower total cost of ownership for the customer’s workload.
AI customers are not buying cheap transistors. They are buying better AI economics.
V. Cost per transistor was the wrong mental model
The 2021 debate spent a lot of time on whether cost per transistor had stopped falling. That question is real, but it is incomplete.
For advanced customers the decision is not “is each transistor cheaper?” The decision is “does the full chip or system create enough value to justify the node?” A node that costs more per transistor can still be the rational choice if the end product earns more, costs less to run, or unlocks an experience that older silicon cannot.
Cost per transistor
Question: is each transistor cheaper at the next node?
If no: demand for the next node weakens, foundry margins compress.
Limit: ignores what the customer actually monetises.
System advantage
Question: does the chip’s performance, power, area, and packaging earn enough product value?
If yes: the customer pays for the node and pulls more of TSMC’s capacity.
Result: 3nm and 5nm dominate wafer revenue.3
Apple pays for performance per watt and battery life on phones, tablets, watches, and laptops. Nvidia pays for AI accelerator performance, power, and packaging integration. AMD pays for server TCO and performance per watt. Hyperscalers pay for custom silicon that reduces long-term data-center cost. Networking and custom-silicon companies pay for bandwidth, power, and density.
The cost per transistor matters at the margin. The system advantage decides the order.
The customer does not monetise transistors. The customer monetises system advantage.
VI. Packaging became additive, not dilutive
The 2021 bear case suggested that 3D packaging and chiplets would reduce the value of leading-edge monolithic scaling. The SemiAnalysis rebuttal argued the opposite: packaging allows more leading-edge silicon content to sit inside a single product, raising the total demand for TSMC’s most advanced manufacturing.1
The 2026 evidence sits firmly with the additive view. TSMC’s 2026 North America Technology Symposium and 2025 Annual Report describe CoWoS expansion, SoIC 3D stacking, InFO, and COUPE for silicon photonics as part of a system-level manufacturing platform around the most advanced logic nodes. Reuters reported TSMC plans roughly nine phases of wafer-fab and advanced-packaging facilities in 2026.456
AI chips are no longer just chips. They are systems in packages, and TSMC sells the manufacturing layer for most of them.
VII. CoWoS is the toll booth
The clearest 2026 evidence that packaging widens rather than narrows TSMC’s moat is CoWoS. AI accelerators need logic and HBM close together. HBM is not useful if it cannot be packaged tightly against compute. CoWoS, TSMC’s advanced 2.5D packaging family, has become one of the defining bottlenecks of the AI hardware cycle.
At its 2026 North America Technology Symposium, TSMC described CoWoS scaling to support more compute and memory in a single package. Reporting on the symposium noted 5.5-reticle CoWoS in production and plans for 14-reticle CoWoS by 2028, capable of integrating roughly 10 large compute dies and 20 HBM stacks, with even larger configurations after 2029.5
The transmission is mechanical. A GPU vendor without enough CoWoS capacity cannot ship enough accelerators. A hyperscaler without accelerators cannot build enough AI compute. A model company without compute cannot scale product usage.
In the AI era, the bottleneck is not only who designs the chip. It is who can package it at scale.
VIII. TSMC is selling capacity certainty
Pricing power is not only a function of process leadership. It is also a function of who can promise supply. AI customers need the best node, but they also need wafer starts, packaging slots, yield stability, ramp predictability, delivery timing, roadmap coordination, supply-chain confidentiality, and customer-specific support across multi-year programs.
Reuters reported in 2026 that TSMC plans roughly nine phases of wafer-fab and advanced-packaging facilities, with the company expecting the global semiconductor market to exceed US$1.5T by 2030, with AI and HPC expected to account for around 55%, smartphones around 20%, and automotive around 10%.6
That kind of capacity build-out is a strategic asset for customers, not just for TSMC. When every major AI roadmap is competing for the same advanced-node and packaging windows, the foundry that can credibly commit to capacity becomes a planning layer inside the customer’s own roadmap.
Capacity is strategy when every major AI roadmap competes for the same advanced-node and packaging bottlenecks.
IX. The roadmap keeps extending the moat
Moore’s Law slowing does not mean TSMC’s innovation stops. It means innovation spreads across transistor architecture, backside power delivery, design-technology co-optimisation, advanced packaging, 3D stacking, optical I/O, and specialty technologies. The 2026 Technology Symposium and Q1 2026 results describe a roadmap that runs across all of these.25
Reporting on TSMC’s 2026 symposium notes that 2nm entered high-volume manufacturing in Q4 2025, with N2P and A16 scheduled for second-half 2026, A13 introduced for 2029, A12 previewed with Super Power Rail backside power for AI/HPC applications, and N2U targeted for production in 2028. CoWoS, SoIC, InFO, and COUPE were described as the packaging and interconnect platforms layered on top.5
The moat is not one node. It is a manufacturing system.
X. ASML shows why AI pulls the whole stack
Lithography is the layer underneath all of this, and ASML’s own framing reinforces the AI pull on advanced logic and memory. ASML’s 2025 Annual Report strategic section describes AI as requiring “leading-edge, high-performance processor chips” and a “significant increase in DRAM” relative to traditional compute architectures, with strong AI growth enabled by advanced Logic and AI-related DRAM, and lithography intensity expected to be favourable as advanced Logic and DRAM capacity expand through 2030.7
That is the wider physical picture. AI does not only pull on Nvidia. It pulls on leading-edge logic, DRAM and HBM, lithography, packaging, interconnect, data-center power, test and inspection, and capacity planning. TSMC sits at the centre because TSMC is where the advanced logic, advanced packaging, and HBM integration converge into a physical product.
TSMC sits where AI demand becomes physical.
XI. The toll road analogy
A toll road is valuable not because it owns the destination. It is valuable because traffic must pass through it. TSMC does not own the AI model, Nvidia’s architecture, AMD’s architecture, Apple’s product design, hyperscaler software, or the HBM stacks themselves. But TSMC owns or controls critical layers of leading-edge manufacturing, advanced packaging, process integration, yield learning, customer trust, and capacity scale.
Almost every serious AI hardware roadmap eventually has to pass through TSMC’s manufacturing, packaging, yield, and capacity system.
XII. Glossary
The vocabulary around AI-era foundry economics has expanded well beyond “wafer” and “node.” A short reference.
- Foundry
- A company that manufactures chips designed by other companies.
- Wafer
- The thin silicon disk on which chips are fabricated.
- Gross margin
- Revenue left after the cost of goods sold.
- Advanced node
- A leading manufacturing process such as 7nm, 5nm, 3nm, or 2nm.
- HPC
- High-performance computing, including AI accelerators and data-center chips.
- CoWoS
- TSMC’s advanced 2.5D packaging family used to integrate logic and HBM.
- HBM
- High-bandwidth memory placed near AI accelerators.
- Interposer
- A layer that connects logic dies and memory in advanced packages.
- SoIC
- TSMC’s 3D stacking technology for logic-on-logic integration.
- InFO
- TSMC’s integrated fan-out packaging family.
- COUPE
- TSMC’s Compact Universal Photonic Engine for optical integration.
- DTCO
- Design-technology co-optimisation across architecture and process.
- Backside power
- Power delivery routed on the back side of the wafer to improve performance and efficiency.
- Reticle
- The lithography exposure field size; large advanced packages are often described in reticle multiples.
- Yield
- The percentage of manufactured chips that work to specification.
XIII. What could break the thesis?
Pricing-power stories age badly when they are told without their risks. The toll-road framing has several.
- Taiwan geopolitics. Concentration of leading-edge logic and packaging in Taiwan remains the most systemic risk in semiconductors. Any major disruption would not only hit TSMC; it would dislocate global AI and computing supply chains.
- Overseas fabs. Arizona, Japan, and Germany improve resilience, but at the cost of higher capex, slower ramp learning, and more complex coordination, which can pressure margins.
- Customer concentration. AI demand is concentrated in a small set of GPU and custom-silicon companies and a few hyperscalers. A meaningful pullback by any of them would show up quickly in HPC mix.3
- Foundry competition. Intel Foundry and Samsung Foundry continue to invest. Neither has caught up in advanced logic or packaging at scale, but the strategic intent is real.
- Packaging bottlenecks. CoWoS and other advanced packaging steps can themselves become constraints. TSMC is expanding capacity, but the bottleneck can move year to year.5
- Overshoot risk. If AI demand softens or shifts toward inference-heavy designs that need less leading-edge compute per dollar, CoWoS and advanced-node capacity additions could overshoot.
- Physical limits. Power, water, labour, land, and export controls all constrain how fast TSMC can grow in any single geography.
- ASIC mix shift. Hyperscaler custom silicon may change which customers pay top dollar for which nodes and packaging, even if the total pull remains strong.
- Adjacent value capture. HBM vendors, substrate suppliers, equipment makers, and EDA companies capture serious value too. The toll road is not the only paid layer.
- AI monetisation lag. If AI infrastructure capex outruns AI revenue for too long, the customer base buying TSMC’s most advanced output gets stress-tested.
- Political pressure. TSMC may face increasing political pressure to globalise capacity at lower returns, which would soften margin power even if process leadership holds.
The risks do not prove TSMC lacks pricing power. They prove the world is trying to diversify because TSMC is too important.
XIV. What to watch
If the toll-road thesis is right, certain things should keep showing up in disclosures, reports, and supply-chain coverage. If the thesis is wrong, these are also where the cracks will appear first.
- Q2 2026 gross margin delivery vs guidance.
- HPC share of revenue.
- Advanced-node revenue mix (7nm and below).
- 3nm and 2nm ramp pace.
- N2P and A16 production timing.
- A13, A12, and N2U roadmap execution.
- CoWoS capacity expansion announcements.
- 14-reticle CoWoS progress.
- SoIC adoption in commercial products.
- COUPE optical I/O progress.
- Capex allocation to advanced packaging.
- Arizona yield and cost performance.
- Customer concentration trajectory.
- Nvidia, AMD, Broadcom, Apple, and hyperscaler demand.
- HBM supplier alignment with CoWoS slots.
- Export controls and trade policy shifts.
- AI infrastructure monetisation reality.
- Intel Foundry and Samsung Foundry competitive progress.
XV. The foundry toll road
Morgan Stanley’s 2021 mistake was treating TSMC like a commodity wafer supplier.
In 2026, TSMC looks more like the toll road for AI compute. Transistors may no longer get cheaper the old way, but AI customers are not buying cheap transistors. They are buying performance-per-watt. They are buying CoWoS capacity. They are buying HBM integration. They are buying yield. They are buying scale. They are buying trust.
The 2021 piece argued that TSMC was a technology innovator, not a generic enabler. The 2026 evidence widens that point. TSMC is not only the most advanced logic manufacturer in the world. It is the manufacturing system around which AI accelerators get designed in the first place.
The next decade will test how far that toll road can extend. The risks are real. The geographic concentration, the customer concentration, the packaging bottlenecks, and the political pressure are not going away. But the simple test the 2021 thesis was supposed to fail keeps producing the same answer.
A company with collapsing pricing power does not guide 65.5% to 67.5% gross margin into its most advanced capacity.2 A foundry losing relevance does not see HPC become 61% of its revenue.3 A manufacturing layer that customers can route around does not become the visible bottleneck in their AI roadmaps.5
TSMC’s moat is not one node. It is a manufacturing system. And in 2026, that system is the foundry toll road for AI compute.
1 Patel, D. (Jun 2021). Morgan Stanley Just Reduced TSMC’s Value By $25B While Demonstrating A Complete Lack of Semiconductor Knowledge. SemiAnalysis. Historical anchor for the 2021 Morgan Stanley downgrade framing, including margin compression, cost-per-transistor scaling, 5G maturity, 3D packaging/chiplets, and the rebuttal that TSMC is a technology innovator whose customers pay for performance, power efficiency, and product value. Used as inspiration only. No content, structure, or charts reproduced.
2 TSMC (2026). First quarter 2026 results. Q1 2026 revenue US$35.9B, gross margin 66.2%, operating margin 58.1%, net profit margin 50.5%, Q2 2026 revenue guidance US$39.0B–40.2B, Q2 gross-margin guidance 65.5%–67.5%, and 2026 full-year revenue growth framed at close to mid-30s percent in US-dollar terms.
3 TSMC (2026). Q1 2026 management presentation and transcript. Platform mix: HPC 61%, smartphone 26%, IoT 6%, automotive 4%, DCE 1%. Wafer-revenue mix by node: 3nm 25%, 5nm 36%, 7nm 13%, advanced technologies at 7nm and below 74% of wafer revenue.
4 TSMC. 2025 Annual Report. Robust AI-related demand throughout 2025, non-AI end markets only mildly recovered, advanced packaging and 3D stacking investment, and the role of CoWoS, InFO, SoIC, and COUPE in supporting AI/HPC and specialty technologies.
5 TSMC (2026). 2026 North America Technology Symposium. N2 2nm HVM in Q4 2025, N2P and A16 production timing for H2 2026, A13 introduced for 2029, A12 with Super Power Rail backside power for AI/HPC applications, N2U targeted for production in 2028, plus CoWoS expansion including 5.5-reticle today and 14-reticle by 2028 supporting roughly 10 compute dies and 20 HBM stacks, with larger configurations after 2029, and SoIC, InFO, and COUPE positioning.
6 Reuters (May 2026). TSMC says global chip market to hit US$1.5T by 2030, AI drives growth. Reporting on TSMC’s 2030 market outlook (AI/HPC ~55%, smartphone ~20%, automotive ~10%) and on TSMC’s plan for roughly nine phases of wafer fab and advanced packaging facilities in 2026.
7 ASML (2025). 2025 Annual Report, strategic report section. AI requires leading-edge high-performance processors and a significant increase in DRAM versus traditional compute architectures; strong AI growth enabled by advanced Logic and AI-related DRAM; lithography intensity favourable as advanced Logic and DRAM capacity expand through 2030.
- The Other Leading Edge. Companion essay on GlobalFoundries as the foundry for specialty AI infrastructure: photonics, RF, power, FD-SOI, eMRAM.
- The AI Memory Wall. DRAM, HBM, packaging, and semicap as the new centre of computing.
- The AI Memory Tax. AI servers repricing DRAM, NAND, and consumer electronics.
- When AI Runs Out of Copper. Optical I/O, co-packaged optics, and the race to replace copper with light.
- The Dry Resist War. Patterning as a strategic process technology for AI-era chipmaking.
- The Density Illusion. Why Moore’s Law became a system problem.
- The Custom Silicon Flywheel. Hyperscalers turning their biggest workloads into chips.
- Nvidia’s Earnings Quality Test. AI capex, customer concentration, and durability of revenue.
- Nvidia Built the AI Factory Anyway. Vertical system integration as the new moat.
- The Inference Efficiency War. Qualcomm AI200/AI250 and cost-per-token inference infrastructure.
- The Boring Back-End Boom. Mature nodes, wirebonding, and packaging becoming strategic again.
- The AI Field Manual. Reference layer for the AI stack: hardware, memory, models, agents, safety, economics.
This is Essay No. 026. The topics: intelligence, AI, systems, knowledge, and the questions underneath the questions everyone else is asking. If you read this far and disagreed with any part of it, write to me. I read everything.